1 diff -Narup linux-2.4.31-orig/drivers/net/Config.in linux-2.4.31/drivers/net/Config.in
2 --- linux-2.4.31-orig/drivers/net/Config.in 2005-01-19 06:09:56.000000000 -0800
3 +++ linux-2.4.31/drivers/net/Config.in 2005-08-03 09:52:16.000000000 -0700
4 @@ -116,6 +116,19 @@ if [ "$CONFIG_NET_ETHERNET" = "y" ]; the
5 dep_tristate ' SMC Ultra support' CONFIG_ULTRA $CONFIG_ISA
6 dep_tristate ' SMC Ultra32 EISA support' CONFIG_ULTRA32 $CONFIG_EISA
7 dep_tristate ' SMC 9194 support' CONFIG_SMC9194 $CONFIG_ISA
8 + tristate ' SMC 91111 support' CONFIG_SMC91111
9 + if [ "$CONFIG_SMC91111" != "n" ]; then
10 + bool ' Advanced configuration options for SMC91111' CONFIG_SMC91111_ADVANCED
11 + if [ "$CONFIG_SMC91111_ADVANCED" = "n" ]; then
12 + define_bool CONFIG_SMC91111_BYTE_SWAP n
13 + define_bool CONFIG_SMC91111_USE_8_BIT y
14 + define_bool CONFIG_SMC91111_USE_32_BIT y
16 + bool ' Byte swap device accesses' CONFIG_SMC91111_BYTE_SWAP
17 + bool ' Allow 8 bit device accesses' CONFIG_SMC91111_USE_8_BIT
18 + bool ' Allow 32 bit device accesses' CONFIG_SMC91111_USE_32_BIT
22 bool ' Racal-Interlan (Micom) NI cards' CONFIG_NET_VENDOR_RACAL
23 if [ "$CONFIG_NET_VENDOR_RACAL" = "y" ]; then
24 diff -Narup linux-2.4.31-orig/drivers/net/Makefile linux-2.4.31/drivers/net/Makefile
25 --- linux-2.4.31-orig/drivers/net/Makefile 2005-01-19 06:09:56.000000000 -0800
26 +++ linux-2.4.31/drivers/net/Makefile 2005-08-03 10:17:28.000000000 -0700
27 @@ -139,6 +139,7 @@ obj-$(CONFIG_SHAPER) += shaper.o
28 obj-$(CONFIG_SK_G16) += sk_g16.o
29 obj-$(CONFIG_HP100) += hp100.o
30 obj-$(CONFIG_SMC9194) += smc9194.o
31 +obj-$(CONFIG_SMC91111) += smc91111.o
32 obj-$(CONFIG_ARM_AM79C961A) += am79c961a.o
33 obj-$(CONFIG_ARM_ETHERH) += 8390.o
34 obj-$(CONFIG_WD80x3) += wd.o 8390.o
35 diff -Narup linux-2.4.31-orig/drivers/net/smc91111.c linux-2.4.31/drivers/net/smc91111.c
36 --- linux-2.4.31-orig/drivers/net/smc91111.c 1969-12-31 16:00:00.000000000 -0800
37 +++ linux-2.4.31/drivers/net/smc91111.c 2005-08-03 09:52:34.000000000 -0700
39 +/*------------------------------------------------------------------------
41 + . This is a driver for SMSC's 91C111 single-chip Ethernet device.
43 + . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
44 + . Developed by Simple Network Magic Corporation (SNMC)
45 + . Copyright (C) 1996 by Erik Stahlman (ES)
47 + . This program is free software; you can redistribute it and/or modify
48 + . it under the terms of the GNU General Public License as published by
49 + . the Free Software Foundation; either version 2 of the License, or
50 + . (at your option) any later version.
52 + . This program is distributed in the hope that it will be useful,
53 + . but WITHOUT ANY WARRANTY; without even the implied warranty of
54 + . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
55 + . GNU General Public License for more details.
57 + . You should have received a copy of the GNU General Public License
58 + . along with this program; if not, write to the Free Software
59 + . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
61 + . Information contained in this file was obtained from the LAN91C111
62 + . manual from SMC. To get a copy, if you really want one, you can find
63 + . information under www.smsc.com.
66 + . "Features" of the SMC chip:
67 + . Integrated PHY/MAC for 10/100BaseT Operation
68 + . Supports internal and external MII
69 + . Integrated 8K packet memory
70 + . EEPROM interface for configuration
73 + . io = for the base address
75 + . nowait = 0 for normal wait states, 1 eliminates additional wait states
78 + . Erik Stahlman ( erik@vt.edu )
79 + . Daris A Nevil ( dnevil@snmc.com )
81 + . Arnaldo Carvalho de Melo <acme@conectiva.com.br>
83 + . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
86 + . o SMSC LAN91C111 databook (www.smsc.com)
87 + . o smc9194.c by Erik Stahlman
88 + . o skeleton.c by Donald Becker ( becker@scyld.com )
91 + . 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet
92 + . 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ"
93 + . 04/25/01 Daris A Nevil Initial public release through SMSC
94 + . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
95 + . 08/22/01 Scott Anderson Merge changes from smc9194 to smc91111
96 + ----------------------------------------------------------------------------*/
98 +// Use power-down feature of the chip
104 + . 0 for normal operation
105 + . 1 for slightly more details
106 + . >2 for various levels of increasingly useless information
107 + . 2 for interrupt tracking, status flags
108 + . 3 for packet info
109 + . 4 for complete packet dumps
115 +static const char version[] =
116 + "smc91111.c:v1.0saa 08/22/01 by Daris A Nevil (dnevil@snmc.com)\n";
118 +#include <linux/module.h>
119 +#include <linux/version.h>
120 +#include <linux/kernel.h>
121 +#include <linux/sched.h>
122 +#include <linux/types.h>
123 +#include <linux/fcntl.h>
124 +#include <linux/interrupt.h>
125 +#include <linux/ptrace.h>
126 +#include <linux/ioport.h>
127 +#include <linux/in.h>
128 +#include <linux/slab.h>
129 +#include <linux/string.h>
130 +#include <linux/init.h>
131 +#include <asm/bitops.h>
133 +#include <linux/errno.h>
134 +#include <linux/delay.h>
136 +#include <linux/netdevice.h>
137 +#include <linux/etherdevice.h>
138 +#include <linux/skbuff.h>
140 +#ifdef CONFIG_SYSCTL
141 +#include <linux/proc_fs.h>
142 +#include <linux/sysctl.h>
145 +#include "smc91111.h"
150 + .the LAN91C111 can be at any of the following port addresses. To change,
151 + .for a slightly different card, you can add it to the array. Keep in
152 + .mind that the array must end in zero.
154 +static unsigned int smc_portlist[] __initdata = {
155 + 0x200, 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x2E0,
156 + 0x300, 0x320, 0x340, 0x360, 0x380, 0x3A0, 0x3C0, 0x3E0, 0
159 +#endif /* CONFIG_ISA */
161 +static struct net_device *global_dev = NULL;
162 +#ifndef SMC91111_BASE_ADDR
163 +# define SMC91111_BASE_ADDR -1
165 +static int io = SMC91111_BASE_ADDR;
166 +#ifndef SMC91111_IRQ
167 +# define SMC91111_IRQ -1
169 +static int irq = SMC91111_IRQ;
170 +static int nowait = 1; //Haup=>
172 +MODULE_PARM(io, "i");
173 +MODULE_PARM(irq, "i");
174 +MODULE_PARM(nowait, "i");
175 +MODULE_PARM_DESC(io, "SMC 91111 I/O base address");
176 +MODULE_PARM_DESC(irq, "SMC 91111 IRQ number");
179 + . Wait time for memory to be free. This probably shouldn't be
180 + . tuned that much, as waiting for this means nothing else happens
183 +#define MEMORY_WAIT_TIME 16
186 +#define PRINTK3(args...) printk(args)
188 +#define PRINTK3(args...)
192 +#define PRINTK2(args...) printk(args)
194 +#define PRINTK2(args...)
198 +#define PRINTK(args...) printk(args)
200 +#define PRINTK(args...)
204 +/*------------------------------------------------------------------------
206 + . The internal workings of the driver. If you are changing anything
207 + . here with the SMC stuff, you should have the datasheet and know
208 + . what you are doing.
210 + -------------------------------------------------------------------------*/
211 +#define CARDNAME "LAN91C111"
213 +// Memory sizing constant
214 +#define LAN91C111_MEMORY_MULTIPLIER (1024*2)
216 +/* store this information for the driver.. */
219 + // these are things that the kernel wants me to keep, so users
220 + // can find out semi-useless statistics of how well the card is
222 + struct net_device_stats stats;
224 + // If I have to wait until memory is available to send
225 + // a packet, I will store the skbuff here, until I get the
226 + // desired memory. Then, I'll send it out and free it.
227 + struct sk_buff * saved_skb;
229 + // This keeps track of how many packets that I have
230 + // sent out. When an TX_EMPTY interrupt comes, I know
231 + // that all of these have been sent.
232 + int packets_waiting;
234 + // Set to true during the auto-negotiation sequence
235 + int autoneg_active;
237 + // Address of our PHY port
243 + // Last contents of PHY Register 18
246 + // Contains the current active transmission mode
249 + // Contains the current active receive mode
252 + // Contains the current active receive/phy mode
256 +#ifdef CONFIG_SYSCTL
258 + // Root directory /proc/sys/dev
259 + // Second entry must be null to terminate the table
260 + ctl_table root_table[2];
262 + // Directory for this device /proc/sys/dev/ethX
263 + // Again the second entry must be zero to terminate
264 + ctl_table eth_table[2];
266 + // This is the parameters (file) table
267 + ctl_table param_table[CTL_SMC_LAST_ENTRY];
269 + // Saves the sysctl header returned by register_sysctl_table()
270 + // we send this to unregister_sysctl_table()
271 + struct ctl_table_header *sysctl_header;
273 + // Parameter variables (files) go here
274 + char ctl_info[1024];
330 +#endif // SMC_DEBUG > 0
333 +#endif // CONFIG_SYSCTL
338 +/*-----------------------------------------------------------------
340 + . The driver can be entered at any of the following entry points.
342 + .------------------------------------------------------------------ */
345 + . The kernel calls this function when someone wants to use the device,
346 + . typically 'ifconfig ethX up'.
348 +static int smc_open(struct net_device *dev);
351 + . Our watchdog timed out. Called by the networking layer
353 +static void smc_timeout(struct net_device *dev);
356 + . This is called by the kernel in response to 'ifconfig ethX down'. It
357 + . is responsible for cleaning up everything that the open routine
358 + . does, and maybe putting the card into a powerdown state.
360 +static int smc_close(struct net_device *dev);
363 + . This routine allows the proc file system to query the driver's
366 +static struct net_device_stats * smc_query_statistics( struct net_device *dev);
369 + . Finally, a call to set promiscuous mode ( for TCPDUMP and related
370 + . programs ) and multicast modes.
372 +static void smc_set_multicast_list(struct net_device *dev);
377 +static int crc32( char * s, int length );
380 + . Configures the PHY through the MII Management interface
382 +static void smc_phy_configure(struct net_device* dev);
384 +/*---------------------------------------------------------------
386 + . Interrupt level calls..
388 + ----------------------------------------------------------------*/
391 + . Handles the actual interrupt
393 +static void smc_interrupt(int irq, void *, struct pt_regs *regs);
395 + . This is a separate procedure to handle the receipt of a packet, to
396 + . leave the interrupt code looking slightly cleaner
398 +inline static void smc_rcv( struct net_device *dev );
400 + . This handles a TX interrupt, which is only called when an error
401 + . relating to a packet is sent.
403 +inline static void smc_tx( struct net_device * dev );
406 + . This handles interrupts generated from PHY register 18
408 +static void smc_phy_interrupt(struct net_device* dev);
411 + ------------------------------------------------------------
413 + . Internal routines
415 + ------------------------------------------------------------
419 + . Test if a given location contains a chip, trying to cause as
420 + . little damage as possible if it's not a SMC chip.
422 +static int smc_probe(struct net_device *dev, unsigned long ioaddr);
425 + . A rather simple routine to print out a packet for debugging purposes.
428 +static void print_packet( byte *, int );
431 +#define tx_done(dev) 1
433 +/* this is called to actually send the packet to the chip */
434 +static void smc_hardware_send_packet( struct net_device * dev );
436 +/* Since I am not sure if I will have enough room in the chip's ram
437 + . to store the packet, I call this routine, which either sends it
438 + . now, or generates an interrupt when the card is ready for the
440 +static int smc_wait_to_send_packet( struct sk_buff * skb, struct net_device *dev );
442 +/* this does a soft reset on the device */
443 +static void smc_reset( struct net_device* dev );
445 +/* Enable Interrupts, Receive, and Transmit */
446 +static void smc_enable( struct net_device *dev );
448 +/* this puts the device in an inactive state */
449 +static void smc_shutdown( unsigned long ioaddr );
451 +/* This routine will find the IRQ of the driver if one is not
452 + . specified in the input to the device. */
453 +static int smc_findirq( unsigned long ioaddr );
455 +/* Routines to Read and Write the PHY Registers across the
456 + MII Management Interface
459 +static word smc_read_phy_register(unsigned long ioaddr,
460 + byte phyaddr, byte phyreg);
461 +static void smc_write_phy_register(unsigned long ioaddr,
462 + byte phyaddr, byte phyreg, word phydata);
465 + Initilizes our device's sysctl proc filesystem
468 +#ifdef CONFIG_SYSCTL
469 +static void smc_sysctl_register(struct net_device *dev);
470 +static void smc_sysctl_unregister(struct net_device *dev);
471 +#endif /* CONFIG_SYSCTL */
474 + . Function: smc_reset( struct net_device* dev )
476 + . This sets the SMC91111 chip to its normal state, hopefully from whatever
477 + . mess that any other DOS driver has put it in.
479 + . Maybe I should reset more registers to defaults in here? SOFTRST should
483 + . 1. send a SOFT RESET
484 + . 2. wait for it to finish
485 + . 3. enable autorelease mode
486 + . 4. reset the memory management unit
487 + . 5. clear all interrupts
490 +static void smc_reset( struct net_device* dev )
492 + //struct smc_local *lp = (struct smc_local *)dev->priv;
493 + unsigned long ioaddr = dev->base_addr;
495 + PRINTK2("%s:smc_reset\n", dev->name);
497 + /* This resets the registers mostly to defaults, but doesn't
498 + affect EEPROM. That seems unnecessary */
499 + SMC_SELECT_BANK( 0 );
500 + SMC_SET_RCR( RCR_SOFTRST );
502 + /* Setup the Configuration Register */
503 + /* This is necessary because the CONFIG_REG is not affected */
504 + /* by a soft reset */
506 + SMC_SELECT_BANK( 1 );
507 + SMC_SET_CONFIG( CONFIG_DEFAULT );
509 + /* Setup for fast accesses if requested */
510 + /* If the card/system can't handle it then there will */
511 + /* be no recovery except for a hard reset or power cycle */
514 + SMC_SET_CONFIG( SMC_GET_CONFIG() | CONFIG_NO_WAIT );
517 + /* Release from possible power-down state */
518 + /* Configuration register is not affected by Soft Reset */
519 + SMC_SELECT_BANK( 1 );
520 + SMC_SET_CONFIG( SMC_GET_CONFIG() | CONFIG_EPH_POWER_EN );
523 + SMC_SELECT_BANK( 0 );
525 + /* this should pause enough for the chip to be happy */
528 + /* Disable transmit and receive functionality */
529 + SMC_SET_RCR( RCR_CLEAR );
530 + SMC_SET_TCR( TCR_CLEAR );
532 + /* set the control register to automatically
533 + release successfully transmitted packets, to make the best
534 + use out of our limited memory */
535 + SMC_SELECT_BANK( 1 );
536 + SMC_SET_CTL( SMC_GET_CTL() | CTL_AUTO_RELEASE );
538 + /* Reset the MMU */
539 + SMC_SELECT_BANK( 2 );
540 + SMC_SET_MMU_CMD( MC_RESET );
542 + /* Note: It doesn't seem that waiting for the MMU busy is needed here,
543 + but this is a place where future chipsets _COULD_ break. Be wary
544 + of issuing another MMU command right after this */
546 + /* Disable all interrupts */
547 + SMC_SET_INT_MASK( 0 );
551 + . Function: smc_enable
552 + . Purpose: let the chip talk to the outside work
554 + . 1. Enable the transmitter
555 + . 2. Enable the receiver
556 + . 3. Enable interrupts
558 +static void smc_enable( struct net_device *dev )
560 + unsigned long ioaddr = dev->base_addr;
561 + struct smc_local *lp = (struct smc_local *)dev->priv;
563 + PRINTK2("%s:smc_enable\n", dev->name);
565 + SMC_SELECT_BANK( 0 );
566 + /* see the header file for options in TCR/RCR DEFAULT*/
567 + SMC_SET_TCR( lp->tcr_cur_mode );
568 + SMC_SET_RCR( lp->rcr_cur_mode );
570 + /* now, enable interrupts */
571 + SMC_SELECT_BANK( 2 );
572 + SMC_SET_INT_MASK( SMC_INTERRUPT_MASK );
576 + . Function: smc_shutdown
577 + . Purpose: closes down the SMC91xxx chip.
579 + . 1. zero the interrupt mask
580 + . 2. clear the enable receive flag
581 + . 3. clear the enable xmit flags
584 + . (1) maybe utilize power down mode.
585 + . Why not yet? Because while the chip will go into power down mode,
586 + . the manual says that it will wake up in response to any I/O requests
587 + . in the register space. Empirical results do not show this working.
589 +static void smc_shutdown( unsigned long ioaddr )
591 + PRINTK2(CARDNAME ":smc_shutdown\n");
593 + /* no more interrupts for me */
594 + SMC_SELECT_BANK( 2 );
595 + SMC_SET_INT_MASK( 0 );
597 + /* and tell the card to stay away from that nasty outside world */
598 + SMC_SELECT_BANK( 0 );
599 + SMC_SET_RCR( RCR_CLEAR );
600 + SMC_SET_TCR( TCR_CLEAR );
603 + /* finally, shut the chip down */
604 + SMC_SELECT_BANK( 1 );
605 + SMC_SET_CONFIG( SMC_GET_CONFIG() & ~CONFIG_EPH_POWER_EN );
611 + . Function: smc_setmulticast( int ioaddr, int count, dev_mc_list * adds )
613 + . This sets the internal hardware table to filter out unwanted multicast
614 + . packets before they take up memory.
616 + . The SMC chip uses a hash table where the high 6 bits of the CRC of
617 + . address are the offset into the table. If that bit is 1, then the
618 + . multicast packet is accepted. Otherwise, it's dropped silently.
620 + . To use the 6 bits as an offset into the table, the high 3 bits are the
621 + . number of the 8 bit register, while the low 3 bits are the bit within
624 + . This routine is based very heavily on the one provided by Peter Cammaert.
628 +static void smc_setmulticast( unsigned long ioaddr, int count,
629 + struct dev_mc_list * addrs ) {
631 + unsigned char multicast_table[ 8 ];
632 + struct dev_mc_list * cur_addr;
633 + /* table for flipping the order of 3 bits */
634 + unsigned char invert3[] = { 0, 4, 2, 6, 1, 5, 3, 7 };
636 + PRINTK2(CARDNAME ":smc_setmulticast\n");
638 + /* start with a table of all zeros: reject all */
639 + memset( multicast_table, 0, sizeof( multicast_table ) );
642 + for ( i = 0; i < count ; i ++, cur_addr = cur_addr->next ) {
645 + /* do we have a pointer here? */
648 + /* make sure this is a multicast address - shouldn't this
649 + be a given if we have it here ? */
650 + if ( !( *cur_addr->dmi_addr & 1 ) )
653 + /* only use the low order bits */
654 + position = crc32( cur_addr->dmi_addr, 6 ) & 0x3f;
656 + /* do some messy swapping to put the bit in the right spot */
657 + multicast_table[invert3[position&7]] |=
658 + (1<<invert3[(position>>3)&7]);
661 + /* now, the table can be loaded into the chipset */
662 + SMC_SELECT_BANK( 3 );
663 + SMC_SET_MCAST( multicast_table );
667 + Finds the CRC32 of a set of bytes.
668 + Again, from Peter Cammaert's code.
670 +static int crc32( char * s, int length ) {
674 + /* crc polynomial for Ethernet */
675 + const unsigned long poly = 0xedb88320;
676 + /* crc value - preinitialized to all 1's */
677 + unsigned long crc_value = 0xffffffff;
679 + for ( perByte = 0; perByte < length; perByte ++ ) {
683 + for ( perBit = 0; perBit < 8; perBit++ ) {
684 + crc_value = (crc_value>>1)^
685 + (((crc_value^c)&0x01)?poly:0);
694 + . Function: smc_wait_to_send_packet( struct sk_buff * skb, struct net_device * )
696 + . Attempt to allocate memory for a packet, if chip-memory is not
697 + . available, then tell the card to generate an interrupt when it
702 + . o if the saved_skb is not currently null, then drop this packet
703 + . on the floor. This should never happen, because of TBUSY.
704 + . o if the saved_skb is null, then replace it with the current packet,
705 + . o See if I can sending it now.
706 + . o (NO): Enable interrupts and let the interrupt handler deal with it.
707 + . o (YES):Send it now.
709 +static int smc_wait_to_send_packet( struct sk_buff * skb, struct net_device * dev )
711 + struct smc_local *lp = (struct smc_local *)dev->priv;
712 + unsigned long ioaddr = dev->base_addr;
714 + unsigned short numPages;
718 + PRINTK3("%s:smc_wait_to_send_packet\n", dev->name);
720 + netif_stop_queue(dev);
721 + /* Well, I want to send the packet.. but I don't know
722 + if I can send it right now... */
724 + if ( lp->saved_skb) {
725 + /* THIS SHOULD NEVER HAPPEN. */
726 + lp->stats.tx_aborted_errors++;
727 + printk("%s: Bad Craziness - sent packet while busy.\n",
731 + lp->saved_skb = skb;
733 + length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
737 + ** The MMU wants the number of pages to be the number of 256 bytes
738 + ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
740 + ** The 91C111 ignores the size bits, but the code is left intact
741 + ** for backwards and future compatibility.
743 + ** Pkt size for allocating is data length +6 (for additional status
744 + ** words, length and ctl!)
746 + ** If odd size then last byte is included in this header.
748 + numPages = ((length & 0xfffe) + 6);
749 + numPages >>= 8; // Divide by 256
751 + if (numPages > 7 ) {
752 + printk("%s: Far too big packet error. \n", dev->name);
753 + /* freeing the packet is a good thing here... but should
754 + . any packets of this size get down here? */
755 + dev_kfree_skb (skb);
756 + lp->saved_skb = NULL;
757 + /* this IS an error, but, i don't want the skb saved */
758 + netif_wake_queue(dev);
761 + /* either way, a packet is waiting now */
762 + lp->packets_waiting++;
764 + /* now, try to allocate the memory */
765 + SMC_SELECT_BANK( 2 );
766 + SMC_SET_MMU_CMD( MC_ALLOC | numPages );
770 + . wait a short amount of time.. if I can send a packet now, I send
771 + . it now. Otherwise, I enable an interrupt and wait for one to be
774 + . I could have handled this a slightly different way, by checking to
775 + . see if any memory was available in the FREE MEMORY register. However,
776 + . either way, I need to generate an allocation, and the allocation works
777 + . no matter what, so I saw no point in checking free memory.
779 + time_out = MEMORY_WAIT_TIME;
781 + status = SMC_GET_INT();
782 + if ( status & IM_ALLOC_INT ) {
783 + /* acknowledge the interrupt */
784 + SMC_ACK_INT( IM_ALLOC_INT );
787 + } while ( -- time_out );
790 + /* oh well, wait until the chip finds memory later */
791 + SMC_ENABLE_INT( IM_ALLOC_INT );
793 + /* Check the status bit one more time just in case */
794 + /* it snuk in between the time we last checked it */
795 + /* and when we set the interrupt bit */
796 + status = SMC_GET_INT();
797 + if ( !(status & IM_ALLOC_INT) ) {
798 + PRINTK2("%s: memory allocation deferred. \n",
800 + /* it's deferred, but I'll handle it later */
804 + /* Looks like it did sneak in, so disable */
805 + /* the interrupt */
806 + SMC_DISABLE_INT( IM_ALLOC_INT );
808 + /* or YES! I can send the packet now.. */
809 + smc_hardware_send_packet(dev);
810 + netif_wake_queue(dev);
815 + . Function: smc_hardware_send_packet(struct net_device * )
817 + . This sends the actual packet to the SMC9xxx chip.
820 + . First, see if a saved_skb is available.
821 + . ( this should NOT be called if there is no 'saved_skb'
822 + . Now, find the packet number that the chip allocated
823 + . Point the data pointers at it in memory
824 + . Set the length word in the chip's memory
825 + . Dump the packet to chip memory
826 + . Check if a last byte is needed ( odd length packet )
827 + . if so, set the control flag right
828 + . Tell the card to send it
829 + . Enable the transmit interrupt, so I know if it failed
830 + . Free the kernel data if I actually sent it.
832 +static void smc_hardware_send_packet( struct net_device * dev )
834 + struct smc_local *lp = (struct smc_local *)dev->priv;
836 + struct sk_buff * skb = lp->saved_skb;
838 + unsigned long ioaddr;
841 + PRINTK3("%s:smc_hardware_send_packet\n", dev->name);
843 + ioaddr = dev->base_addr;
846 + PRINTK("%s: In XMIT with no packet to send \n", dev->name);
849 + length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
852 + /* If I get here, I _know_ there is a packet slot waiting for me */
853 + packet_no = SMC_GET_AR();
854 + if ( packet_no & AR_FAILED ) {
855 + /* or isn't there? BAD CHIP! */
856 + printk(KERN_DEBUG "%s: Memory allocation failed. \n",
858 + dev_kfree_skb_any(skb);
859 + lp->saved_skb = NULL;
860 + netif_wake_queue(dev);
864 + /* we have a packet address, so tell the card to use it */
865 + SMC_SET_PN( packet_no );
867 + /* point to the beginning of the packet */
868 + SMC_SET_PTR( PTR_AUTOINC );
870 + PRINTK3("%s: Trying to xmit packet of length %x\n",
871 + dev->name, length);
874 + printk("Transmitting Packet\n");
875 + print_packet( buf, length );
878 + /* send the packet length ( +6 for status, length and ctl byte )
879 + and the status word ( set to zeros ) */
880 +#ifdef CONFIG_SMC91111_USE_32_BIT
881 + SMC_outl( (length +6 ) << 16 , ioaddr + DATA_REG );
883 + SMC_outw( 0, ioaddr + DATA_REG );
884 + /* send the packet length ( +6 for status words, length, and ctl*/
885 + SMC_outw( (length+6), ioaddr + DATA_REG );
888 + /* send the actual data
889 + . I _think_ it's faster to send the longs first, and then
890 + . mop up by sending the last word. It depends heavily
891 + . on alignment, at least on the 486. Maybe it would be
892 + . a good idea to check which is optimal? But that could take
893 + . almost as much time as is saved?
895 +#ifdef CONFIG_SMC91111_USE_32_BIT
896 + SMC_outsl(ioaddr + DATA_REG, buf, length >> 2 );
897 + if ( length & 0x2 )
898 + SMC_outw(*((word *)(buf + (length & 0xFFFFFFFC))),ioaddr +
901 + SMC_outsw(ioaddr + DATA_REG , buf, (length ) >> 1);
902 +#endif // CONFIG_SMC91111_USE_32_BIT
904 + /* Send the last byte, if there is one. */
905 + if ( (length & 1) == 0 ) {
906 + SMC_outw( 0, ioaddr + DATA_REG );
908 + SMC_outw( 0x2000 | buf[length -1 ], ioaddr + DATA_REG );
911 + /* enable the interrupts */
912 + SMC_ENABLE_INT( (IM_TX_INT | IM_TX_EMPTY_INT) );
914 + /* and let the chipset deal with it */
915 + SMC_SET_MMU_CMD( MC_ENQUEUE );
917 + PRINTK2("%s: Sent packet of length %d \n", dev->name, length);
919 + lp->saved_skb = NULL;
920 + dev_kfree_skb_any (skb);
922 + dev->trans_start = jiffies;
924 + /* we can send another packet */
925 + netif_wake_queue(dev);
930 +/*-------------------------------------------------------------------------
933 + | Input parameters:
934 + | dev->base_addr == 0, try to find all possible locations
935 + | dev->base_addr > 0x1ff, this is the address to check
936 + | dev->base_addr == <anything else>, return failure code
939 + | 0 --> there is a device
940 + | anything else, error
942 + ---------------------------------------------------------------------------
944 +static int __init smc_init( void )
948 + PRINTK2(CARDNAME ":smc_init\n");
951 + * Haup=> Set BRCR1 TWT to wait for 7+1=8 SYS_CLK(63MHz) => 126.98ns > 100 ns)
952 + * Changes: 02/09/2004=> reduce Bus Hold Time to 1 SYS_CLK
955 + #define BRCR_REGMEM_BASE 0x70
956 + #define REG_BRCRH0 (BRCR_REGMEM_BASE + 0)
957 + #define REG_BRCRH1 (BRCR_REGMEM_BASE + 1)
958 + #define REG_BRCRH2 (BRCR_REGMEM_BASE + 2)
959 + #define REG_BRCRH3 (BRCR_REGMEM_BASE + 3)
961 + #define REG_BRCR0 (BRCR_REGMEM_BASE + 0x10)
962 + #define REG_BRCR1 (BRCR_REGMEM_BASE + 0x11)
963 + #define REG_BRCR2 (BRCR_REGMEM_BASE + 0x12)
964 + #define REG_BRCR3 (BRCR_REGMEM_BASE + 0x13)
965 + #define REG_BIUCR (BRCR_REGMEM_BASE + 0x2A)
967 + #define __to_asm_token(s) #s
969 + #define MF_DCR(rn) __mfdcr_or_dflt(rn, 0)
971 + #define __mfdcr_or_dflt(rn,default_rval) \
972 + ({unsigned int rval; \
974 + rval = default_rval; \
976 + asm volatile("mfdcr %0," __to_asm_token(rn) : "=r" (rval)); \
979 + #define MT_DCR(rn, v) \
981 + asm volatile("mtdcr " __to_asm_token(rn) ",%0" : : "r" (v));}
984 + unsigned int brcr1;
986 + brcr1 = MF_DCR(REG_BRCR1);
987 + printk("smsc91111 org brcr1 = 0x%08x\n", brcr1);
989 + /* set TWT = 7+1 SYS_CLK */
990 + brcr1 = (brcr1 & ~(0x3f<<8)) | (7<<8);
991 + /* set TH = 1 SYS_CLK */
992 + brcr1 = (brcr1 & ~(0x07<<1)) | (0x01<<1);
994 + MT_DCR(REG_BRCR1, brcr1);
995 + brcr1 = MF_DCR(REG_BRCR1);
996 + printk("smsc91111 (brcr1 = 0x%08x) => TWT cycle = %d\n",
998 + ((brcr1 & (0x3f<<8))>>8));
1003 + printk(KERN_WARNING
1004 + CARDNAME": You shouldn't use auto-probing with insmod!\n" );
1008 + printk(CARDNAME ": already initialized.\n");
1012 + global_dev = init_etherdev(0, sizeof(struct smc_local));
1013 + if (!global_dev) {
1014 + printk(CARDNAME ": could not allocate device.\n");
1017 + SET_MODULE_OWNER(global_dev);
1019 + /* copy the parameters from insmod into the device structure */
1021 + global_dev->base_addr = io;
1023 + global_dev->irq = irq;
1024 + global_dev->dma = nowait; // Use DMA field for nowait
1027 + /* try a specific location */
1028 + if (global_dev->base_addr > 0x1ff)
1029 + rtn = smc_probe(global_dev, global_dev->base_addr);
1030 + else if (global_dev->base_addr != 0)
1035 + /* check every ethernet address */
1036 + for (i = 0; smc_portlist[i]; i++) {
1037 + rtn = smc_probe(global_dev, smc_portlist[i]);
1045 + if (global_dev->base_addr == -1) {
1046 + printk(KERN_WARNING
1047 + CARDNAME": SMC91111_BASE_ADDR not set!\n" );
1051 + rtn = smc_probe(global_dev,
1052 + (int)ioremap(global_dev->base_addr,
1057 + printk(CARDNAME ": not found.\n");
1058 + /* couldn't find anything */
1060 + iounmap((void *)global_dev->base_addr);
1062 + kfree(global_dev->priv);
1063 + unregister_netdev(global_dev);
1064 + kfree(global_dev);
1070 +/*----------------------------------------------------------------------
1073 + . This routine has a simple purpose -- make the SMC chip generate an
1074 + . interrupt, so an auto-detect routine can detect it, and find the IRQ,
1075 + ------------------------------------------------------------------------
1077 +int __init smc_findirq( unsigned long ioaddr )
1080 + unsigned long cookie;
1082 + PRINTK2(CARDNAME ":smc_findirq\n");
1084 + /* I have to do a STI() here, because this is called from
1085 + a routine that does an CLI during this process, making it
1086 + rather difficult to get interrupts for auto detection */
1089 + cookie = probe_irq_on();
1092 + * What I try to do here is trigger an ALLOC_INT. This is done
1093 + * by allocating a small chunk of memory, which will give an interrupt
1098 + SMC_SELECT_BANK(2);
1099 + /* enable ALLOCation interrupts ONLY */
1100 + SMC_SET_INT_MASK( IM_ALLOC_INT );
1103 + . Allocate 512 bytes of memory. Note that the chip was just
1104 + . reset so all the memory is available
1106 + SMC_SET_MMU_CMD( MC_ALLOC | 1 );
1109 + . Wait until positive that the interrupt has been generated
1111 + while ( timeout ) {
1114 + int_status = SMC_GET_INT();
1116 + if ( int_status & IM_ALLOC_INT )
1117 + break; /* got the interrupt */
1121 + /* there is really nothing that I can do here if timeout fails,
1122 + as autoirq_report will return a 0 anyway, which is what I
1123 + want in this case. Plus, the clean up is needed in both
1127 + On a fast machine, the status might change before the interrupt
1128 + is given to the processor. This means that the interrupt was
1129 + never detected, and autoirq_report fails to report anything.
1130 + This should fix autoirq_* problems.
1134 + /* and disable all interrupts again */
1135 + SMC_SET_INT_MASK( 0 );
1137 + /* clear hardware interrupts again, because that's how it
1138 + was when I was called... */
1141 + /* and return what I found */
1142 + return probe_irq_off(cookie);
1145 +/*----------------------------------------------------------------------
1146 + . Function: smc_probe( unsigned long ioaddr )
1149 + . Tests to see if a given ioaddr points to an SMC91111 chip.
1150 + . Returns a 0 on success
1153 + . (1) see if the high byte of BANK_SELECT is 0x33
1154 + . (2) compare the ioaddr with the base register's address
1155 + . (3) see if I recognize the chip ID in the appropriate register
1157 + .---------------------------------------------------------------------
1159 +/*---------------------------------------------------------------
1160 + . Here I do typical initialization tasks.
1162 + . o Initialize the structure if needed
1163 + . o print out my vanity message if not done so already
1164 + . o print out what type of hardware is detected
1165 + . o print out the ethernet address
1167 + . o set up my private data
1168 + . o configure the dev structure with my subroutines
1169 + . o actually GRAB the irq.
1170 + . o GRAB the region
1171 + .-----------------------------------------------------------------
1173 +static int __init smc_probe(struct net_device *dev, unsigned long ioaddr)
1175 + int i, memory, retval;
1176 + static unsigned version_printed;
1177 + unsigned int bank;
1179 + const char *version_string;
1180 + const char *if_string = 0;
1183 + word revision_register;
1184 + word base_address_register;
1185 + word memory_info_register;
1187 + PRINTK2(CARDNAME ":smc_probe\n");
1189 + /* Grab the region so that no one else tries to probe our ioports. */
1190 + if (!request_region(ioaddr, SMC_IO_EXTENT, dev->name))
1193 + /* First, see if the high byte is 0x33 */
1194 + bank = SMC_CURRENT_BANK();
1195 + if ( (bank & 0xFF00) != 0x3300 ) {
1196 + if ( (bank & 0xFF) == 0x33 ) {
1198 + ": Detected possible byte-swapped interface"
1199 + " at IOADDR %lx\n", ioaddr);
1204 + /* The above MIGHT indicate a device, but I need to write to further
1206 + SMC_SELECT_BANK(0);
1207 + bank = SMC_CURRENT_BANK();
1208 + if ( (bank & 0xFF00 ) != 0x3300 ) {
1212 + /* well, we've already written once, so hopefully another time won't
1213 + hurt. This time, I need to switch the bank register to bank 1,
1214 + so I can access the base address register */
1215 + SMC_SELECT_BANK(1);
1216 + base_address_register = SMC_GET_BASE();
1217 + base_address_register = ((base_address_register & 0xE000)
1218 + | ((base_address_register & 0x1F00) >> 3));
1219 + if ( (ioaddr & (PAGE_SIZE-1)) != base_address_register ) {
1220 + printk(CARDNAME ": IOADDR %lx doesn't match configuration (%x)."
1221 + "Probably not a SMC chip\n",
1222 + ioaddr, base_address_register );
1223 + /* well, the base address register didn't match. Must not have
1224 + been a SMC chip after all. */
1229 + /* check if the revision register is something that I recognize.
1230 + These might need to be added to later, as future revisions
1231 + could be added. */
1232 + SMC_SELECT_BANK(3);
1233 + revision_register = SMC_GET_REV();
1234 + if ( !chip_ids[ ( revision_register >> 4 ) & 0xF ] ) {
1235 + /* I don't recognize this chip, so... */
1236 + printk(CARDNAME ": IO %lx: Unrecognized revision register:"
1237 + " %x, Contact author. \n",
1238 + ioaddr, revision_register );
1244 + /* at this point I'll assume that the chip is an SMC9xxx.
1245 + It might be prudent to check a listing of MAC addresses
1246 + against the hardware address, or do some other tests. */
1248 + if (version_printed++ == 0)
1249 + printk("%s", version);
1251 + /* fill in some of the fields */
1252 + dev->base_addr = ioaddr;
1255 + . Get the MAC address ( bank 1, regs 4 - 9 )
1257 + SMC_SELECT_BANK( 1 );
1258 + for ( i = 0; i < 6; i += 2 ) {
1261 + address = SMC_inw( ioaddr + ADDR0_REG + i );
1262 + dev->dev_addr[ i + 1] = address >> 8;
1263 + dev->dev_addr[ i ] = address & 0xFF;
1266 + /* get the memory information */
1268 + SMC_SELECT_BANK( 0 );
1269 + memory_info_register = SMC_GET_MIR();
1270 + memory = memory_info_register & (word)0x00ff;
1271 + memory *= LAN91C111_MEMORY_MULTIPLIER;
1274 + Now, I want to find out more about the chip. This is sort of
1275 + redundant, but it's cleaner to have it in both, rather than having
1276 + one VERY long probe procedure.
1278 + SMC_SELECT_BANK(3);
1279 + revision_register = SMC_GET_REV();
1280 + version_string = chip_ids[ ( revision_register >> 4 ) & 0xF ];
1281 + if ( !version_string ) {
1282 + /* I shouldn't get here because this call was done before.... */
1288 + /* now, reset the chip, and put it into a known state */
1292 + . If dev->irq is 0, then the device has to be banged on to see
1293 + . what the IRQ is.
1295 + . This banging doesn't always detect the IRQ, for unknown reasons.
1296 + . a workaround is to reset the chip and try again.
1298 + . Interestingly, the DOS packet driver *SETS* the IRQ on the card to
1299 + . be what is requested on the command line. I don't do that, mostly
1300 + . because the card that I have uses a non-standard method of accessing
1301 + . the IRQs, and because this _should_ work in most configurations.
1303 + . Specifying an IRQ is done with the assumption that the user knows
1304 + . what (s)he is doing. No checking is done!!!!
1307 + if ( dev->irq < 2 ) {
1311 + while ( trials-- ) {
1312 + dev->irq = smc_findirq( ioaddr );
1315 + /* kick the card and try again */
1319 + if (dev->irq == 0 ) {
1320 + printk("%s: Couldn't autodetect your IRQ. Use irq=xx.\n",
1325 + if (dev->irq == 2) {
1326 + /* Fixup for users that don't know that IRQ 2 is really IRQ 9,
1327 + * or don't know which one to set.
1332 + /* now, print out the card info, in a short format.. */
1334 + printk("%s: %s(r:%d) at %#lx IRQ:%d\n", dev->name,
1335 + version_string, revision_register & 0xF, ioaddr, dev->irq );
1336 + printk(" INTF:%s MEM:%db NOWAIT:%d", if_string, memory, dev->dma );
1338 + . Print the Ethernet address
1341 + for (i = 0; i < 5; i++)
1342 + printk("%2.2x:", dev->dev_addr[i] );
1343 + printk("%2.2x \n", dev->dev_addr[5] );
1345 + /* set the private data to zero by default */
1346 + memset(dev->priv, 0, sizeof(struct smc_local));
1348 + /* Fill in the fields of the device structure with ethernet values. */
1351 + /* Grab the IRQ */
1352 + retval = request_irq(dev->irq, &smc_interrupt, 0, dev->name, dev);
1357 + dev->open = smc_open;
1358 + dev->stop = smc_close;
1359 + dev->hard_start_xmit = smc_wait_to_send_packet;
1360 + dev->tx_timeout = smc_timeout;
1361 + dev->watchdog_timeo = HZ/20;
1362 + dev->get_stats = smc_query_statistics;
1363 + dev->set_multicast_list = smc_set_multicast_list;
1368 + release_region(ioaddr, SMC_IO_EXTENT);
1373 +static void print_packet( byte * buf, int length )
1382 + printk("Packet of length %d \n", length );
1385 + lines = length / 16;
1386 + remainder = length % 16;
1388 + for ( i = 0; i < lines ; i ++ ) {
1391 + for ( cur = 0; cur < 8; cur ++ ) {
1396 + printk("%02x%02x ", a, b );
1400 + for ( i = 0; i < remainder/2 ; i++ ) {
1405 + printk("%02x%02x ", a, b );
1415 + * Open and Initialize the board
1417 + * Set up everything, reset the card, etc ..
1420 +static int smc_open(struct net_device *dev)
1422 + struct smc_local *lp = (struct smc_local *)dev->priv;
1423 + unsigned long ioaddr = dev->base_addr;
1424 + int i; /* used to set hw ethernet address */
1426 + PRINTK2("%s:smc_open\n", dev->name);
1428 + /* clear out all the junk that was put here before... */
1429 + memset(dev->priv, 0, sizeof(struct smc_local));
1431 + // Setup the default Register Modes
1432 + lp->tcr_cur_mode = TCR_DEFAULT;
1433 + lp->rcr_cur_mode = RCR_DEFAULT;
1434 + lp->rpc_cur_mode = RPC_DEFAULT;
1436 + // Set default parameters (files)
1437 + lp->ctl_swfdup = 0;
1438 + lp->ctl_ephloop = 0;
1439 + lp->ctl_miiop = 0;
1440 + lp->ctl_autoneg = 1; //1
1441 + lp->ctl_rfduplx = 0; //Haup=> negotiate for HALF?
1442 + lp->ctl_rspeed = 100; //100
1443 + lp->ctl_afduplx = 0; //1
1444 + lp->ctl_aspeed = 100; //100
1445 + lp->ctl_lnkfail = 1;
1446 + lp->ctl_forcol = 0;
1447 + lp->ctl_filtcar = 0;
1449 + /* reset the hardware */
1452 + smc_enable( dev );
1454 + /* Configure the PHY */
1455 + smc_phy_configure(dev);
1458 + According to Becker, I have to set the hardware address
1459 + at this point, because the (l)user can set it with an
1460 + ioctl. Easily done...
1462 + SMC_SELECT_BANK( 1 );
1463 + for ( i = 0; i < 6; i += 2 ) {
1466 + address = dev->dev_addr[ i + 1 ] << 8 ;
1467 + address |= dev->dev_addr[ i ];
1468 + SMC_outw( address, ioaddr + ADDR0_REG + i );
1471 +#ifdef CONFIG_SYSCTL
1472 + smc_sysctl_register(dev);
1473 +#endif /* CONFIG_SYSCTL */
1475 + netif_start_queue(dev);
1479 +/*--------------------------------------------------------
1480 + . Called by the kernel to send a packet out into the void
1481 + . of the net. This routine is largely based on
1482 + . skeleton.c, from Becker.
1483 + .--------------------------------------------------------
1485 +static void smc_timeout(struct net_device *dev)
1487 + struct smc_local *lp = (struct smc_local *)dev->priv;
1489 + PRINTK3("%s:smc_timeout\n", dev->name);
1491 + /* If we get here, some higher level has decided we are broken.
1492 + There should really be a "kick me" function call instead. */
1493 + printk(KERN_WARNING "%s: transmit timed out, %s?\n",
1494 + dev->name, tx_done(dev) ? "IRQ conflict" :
1495 + "network cable problem");
1496 + /* "kick" the adaptor */
1498 + smc_enable( dev );
1501 + /* Reconfiguring the PHY doesn't seem like a bad idea here, but
1502 + * it introduced a problem. Now that this is a timeout routine,
1503 + * we are getting called from within an interrupt context.
1504 + * smc_phy_configure() calls smc_wait_ms() which calls
1505 + * schedule_timeout() which calls schedule(). When schedule()
1506 + * is called from an interrupt context, it prints out
1507 + * "Scheduling in interrupt" and then calls BUG(). This is
1508 + * obviously not desirable. This was worked around by removing
1509 + * the call to smc_phy_configure() here because it didn't seem
1510 + * absolutely necessary. Ultimately, if smc_wait_ms() is
1511 + * supposed to be usable from an interrupt context (which it
1512 + * looks like it thinks it should handle), it should be fixed.
1514 + /* Reconfigure the PHY */
1515 + smc_phy_configure(dev);
1517 + dev->trans_start = jiffies;
1518 + /* clear anything saved */
1519 + if (lp->saved_skb != NULL) {
1520 + dev_kfree_skb (lp->saved_skb);
1521 + lp->saved_skb = NULL;
1523 + ((struct smc_local *)dev->priv)->saved_skb = NULL;
1524 + netif_wake_queue(dev);
1527 +/*--------------------------------------------------------------------
1529 + . This is the main routine of the driver, to handle the device when
1530 + . it needs some attention.
1533 + . first, save state of the chipset
1534 + . branch off into routines to handle each case, and acknowledge
1535 + . each to the interrupt register
1536 + . and finally restore state.
1538 + ---------------------------------------------------------------------*/
1539 +static void smc_interrupt(int irq, void * dev_id, struct pt_regs * regs)
1541 + struct net_device *dev = dev_id;
1542 + unsigned long ioaddr = dev->base_addr;
1543 + struct smc_local *lp = (struct smc_local *)dev->priv;
1549 + /* state registers */
1551 + word saved_pointer;
1553 + PRINTK3("%s: SMC interrupt started \n", dev->name);
1555 + if (dev == NULL) {
1556 + printk(KERN_WARNING "%s: irq %d for unknown device.\n",
1561 + saved_bank = SMC_CURRENT_BANK();
1563 + SMC_SELECT_BANK(2);
1564 + saved_pointer = SMC_GET_PTR();
1566 + /* read the interrupt mask register */
1567 + mask = SMC_GET_INT_MASK();
1569 + /* disable all interrupts */
1570 + SMC_SET_INT_MASK( 0 );
1572 + /* set a timeout value, so I don't stay here forever */
1575 + PRINTK2(KERN_WARNING "%s: MASK IS %x \n", dev->name, mask);
1577 + /* read the status flag, and mask it */
1578 + status = SMC_GET_INT() & mask;
1582 + PRINTK3(KERN_WARNING "%s: Handling interrupt status %x \n",
1583 + dev->name, status);
1585 + if (status & IM_RCV_INT) {
1586 + /* Got a packet(s). */
1587 + PRINTK2(KERN_WARNING
1588 + "%s: Receive Interrupt\n", dev->name);
1590 + } else if (status & IM_TX_INT ) {
1591 + PRINTK2(KERN_WARNING "%s: TX ERROR handled\n",
1594 + // Acknowledge the interrupt
1595 + SMC_ACK_INT( IM_TX_INT );
1596 + } else if (status & IM_TX_EMPTY_INT ) {
1597 + /* update stats */
1598 + SMC_SELECT_BANK( 0 );
1599 + card_stats = SMC_GET_COUNTER();
1600 + /* single collisions */
1601 + lp->stats.collisions += card_stats & 0xF;
1603 + /* multiple collisions */
1604 + lp->stats.collisions += card_stats & 0xF;
1606 + /* these are for when linux supports these statistics */
1608 + SMC_SELECT_BANK( 2 );
1609 + PRINTK2(KERN_WARNING "%s: TX_BUFFER_EMPTY handled\n",
1611 + // Acknowledge the interrupt
1612 + SMC_ACK_INT( IM_TX_EMPTY_INT );
1613 + mask &= ~IM_TX_EMPTY_INT;
1614 + lp->stats.tx_packets += lp->packets_waiting;
1615 + lp->packets_waiting = 0;
1617 + } else if (status & IM_ALLOC_INT ) {
1618 + PRINTK2(KERN_DEBUG "%s: Allocation interrupt \n",
1620 + /* clear this interrupt so it doesn't happen again */
1621 + mask &= ~IM_ALLOC_INT;
1623 + smc_hardware_send_packet( dev );
1625 + /* enable xmit interrupts based on this */
1626 + mask |= ( IM_TX_EMPTY_INT | IM_TX_INT );
1628 + /* and let the card send more packets to me */
1629 + netif_wake_queue(dev);
1631 + PRINTK2("%s: Handoff done successfully.\n",
1633 + } else if (status & IM_RX_OVRN_INT ) {
1634 + lp->stats.rx_errors++;
1635 + lp->stats.rx_fifo_errors++;
1636 + // Acknowledge the interrupt
1637 + SMC_ACK_INT( IM_RX_OVRN_INT );
1638 + } else if (status & IM_EPH_INT ) {
1639 + PRINTK("%s: UNSUPPORTED: EPH INTERRUPT \n",
1641 + } else if (status & IM_MDINT ) {
1642 + smc_phy_interrupt(dev);
1643 + // Acknowledge the interrupt
1644 + SMC_ACK_INT( IM_MDINT );
1645 + } else if (status & IM_ERCV_INT ) {
1646 + PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT \n",
1648 + // Acknowledge the interrupt
1649 + SMC_ACK_INT( IM_ERCV_INT );
1651 + } while ( timeout -- );
1654 + /* restore register states */
1656 + SMC_SELECT_BANK( 2 );
1658 + SMC_SET_INT_MASK( mask );
1660 + PRINTK3( KERN_WARNING "%s: MASK is now %x \n", dev->name, mask);
1661 + SMC_SET_PTR( saved_pointer );
1663 + SMC_SELECT_BANK( saved_bank );
1665 + PRINTK3("%s: Interrupt done\n", dev->name);
1669 +/*-------------------------------------------------------------
1671 + . smc_rcv - receive a packet from the card
1673 + . There is ( at least ) a packet waiting to be read from
1676 + . o Read the status
1677 + . o If an error, record it
1678 + . o otherwise, read in the packet
1679 + --------------------------------------------------------------
1681 +static void smc_rcv(struct net_device *dev)
1683 + struct smc_local *lp = (struct smc_local *)dev->priv;
1684 + unsigned long ioaddr = dev->base_addr;
1685 + int packet_number;
1687 + word packet_length;
1689 + PRINTK3("%s:smc_rcv\n", dev->name);
1691 + /* assume bank 2 */
1693 + packet_number = SMC_GET_RXFIFO();
1695 + if ( packet_number & RXFIFO_REMPTY ) {
1697 + /* we got called , but nothing was on the FIFO */
1698 + PRINTK("%s: WARNING: smc_rcv with nothing on FIFO. \n",
1700 + /* don't need to restore anything */
1704 + /* start reading from the start of the packet */
1705 + SMC_SET_PTR( PTR_READ | PTR_RCV | PTR_AUTOINC );
1707 + /* First two words are status and packet_length */
1708 + status = SMC_inw( ioaddr + DATA_REG );
1709 + packet_length = SMC_inw( ioaddr + DATA_REG );
1711 + packet_length &= 0x07ff; /* mask off top bits */
1713 + PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
1715 + if ( !(status & RS_ERRORS ) ){
1716 + /* do stuff to make a new packet */
1717 + struct sk_buff * skb;
1720 + /* set multicast stats */
1721 + if ( status & RS_MULTICAST )
1722 + lp->stats.multicast++;
1724 + // Allocate enough memory for entire receive frame, to be safe
1725 + skb = dev_alloc_skb( packet_length );
1727 + /* Adjust for having already read the first two words */
1728 + packet_length -= 4;
1730 + if ( skb == NULL ) {
1731 + printk(KERN_NOTICE "%s: Low memory, packet dropped.\n",
1733 + lp->stats.rx_dropped++;
1738 + ! This should work without alignment, but it could be
1739 + ! in the worse case
1742 + skb_reserve( skb, 2 ); /* 16 bit alignment */
1746 + // set odd length for bug in LAN91C111,
1747 + // which never sets RS_ODDFRAME
1748 + data = skb_put( skb, packet_length + 1 );
1750 +#ifdef CONFIG_SMC91111_USE_32_BIT
1751 + PRINTK3(" Reading %d dwords (and %d bytes) \n",
1752 + packet_length >> 2, packet_length & 3 );
1753 + /* QUESTION: Like in the TX routine, do I want
1754 + to send the DWORDs or the bytes first, or some
1755 + mixture. A mixture might improve already slow PIO
1757 + SMC_insl(ioaddr + DATA_REG , data, packet_length >> 2 );
1758 + /* read the left over bytes */
1759 +#ifdef CONFIG_SMC91111_USE_8_BIT
1760 + SMC_insb( ioaddr + DATA_REG, data + (packet_length & 0xFFFFFC),
1761 + packet_length & 0x3 );
1763 + if (packet_length & 0x3)
1765 + unsigned long remaining_data;
1766 + insl(ioaddr + DATA_REG , &remaining_data, 1);
1767 + memcpy(data + (packet_length & 0xFFFFFC),
1768 + &remaining_data, packet_length & 0x3 );
1770 +#endif // CONFIG_SMC91111_USE_8_BIT
1772 + PRINTK3(" Reading %d words and %d byte(s) \n",
1773 + (packet_length >> 1 ), packet_length & 1 );
1774 + SMC_insw(ioaddr + DATA_REG , data, packet_length >> 1);
1776 +#endif // CONFIG_SMC91111_USE_32_BIT
1779 + printk("Receiving Packet\n");
1780 + print_packet( data, packet_length );
1783 + skb->protocol = eth_type_trans(skb, dev );
1785 + dev->last_rx = jiffies;
1786 + lp->stats.rx_packets++;
1787 + lp->stats.rx_bytes += packet_length;
1790 + lp->stats.rx_errors++;
1792 + if ( status & RS_ALGNERR ) lp->stats.rx_frame_errors++;
1793 + if ( status & (RS_TOOSHORT | RS_TOOLONG ) )
1794 + lp->stats.rx_length_errors++;
1795 + if ( status & RS_BADCRC) lp->stats.rx_crc_errors++;
1798 + while ( SMC_GET_MMU_CMD() & MC_BUSY )
1799 + udelay(1); // Wait until not busy
1802 + /* error or good, tell the card to get rid of this packet */
1803 + SMC_SET_MMU_CMD( MC_RELEASE );
1807 +/*************************************************************************
1810 + . Purpose: Handle a transmit error message. This will only be called
1811 + . when an error, because of the AUTO_RELEASE mode.
1814 + . Save pointer and packet no
1815 + . Get the packet no from the top of the queue
1816 + . check if it's valid ( if not, is this an error??? )
1817 + . read the status word
1818 + . record the error
1819 + . ( resend? Not really, since we don't want old packets around )
1820 + . Restore saved values
1821 + ************************************************************************/
1822 +static void smc_tx( struct net_device * dev )
1824 + unsigned long ioaddr = dev->base_addr;
1825 + struct smc_local *lp = (struct smc_local *)dev->priv;
1826 + byte saved_packet;
1831 + PRINTK3("%s:smc_tx\n", dev->name);
1833 + /* assume bank 2 */
1835 + saved_packet = SMC_GET_PN();
1836 + packet_no = SMC_GET_RXFIFO();
1837 + packet_no &= 0x7F;
1839 + /* If the TX FIFO is empty then nothing to do */
1840 + if ( packet_no & TXFIFO_TEMPTY )
1843 + /* select this as the packet to read from */
1844 + SMC_SET_PN( packet_no );
1846 + /* read the first word (status word) from this packet */
1847 + SMC_SET_PTR( PTR_AUTOINC | PTR_READ );
1849 + tx_status = SMC_inw( ioaddr + DATA_REG );
1850 + PRINTK3("%s: TX DONE STATUS: %4x \n", dev->name, tx_status);
1852 + lp->stats.tx_errors++;
1853 + if ( tx_status & TS_LOSTCAR ) lp->stats.tx_carrier_errors++;
1854 + if ( tx_status & TS_LATCOL ) {
1856 + "%s: Late collision occurred on last xmit.\n",
1858 + lp->stats.tx_window_errors++;
1859 + lp->ctl_forcol = 0; // Reset forced collsion
1862 + if ( tx_status & TS_16COL ) { ... }
1865 + if ( tx_status & TS_SUCCESS ) {
1866 + printk("%s: Successful packet caused interrupt \n", dev->name);
1868 + /* re-enable transmit */
1869 + SMC_SELECT_BANK( 0 );
1870 + SMC_SET_TCR( SMC_GET_TCR() | TCR_ENABLE );
1872 + /* kill the packet */
1873 + SMC_SELECT_BANK( 2 );
1874 + SMC_SET_MMU_CMD( MC_FREEPKT );
1876 + /* one less packet waiting for me */
1877 + lp->packets_waiting--;
1879 + /* Don't change Packet Number Reg until busy bit is cleared */
1880 + /* Per LAN91C111 Spec, Page 50 */
1881 + while ( SMC_GET_MMU_CMD() & MC_BUSY );
1883 + SMC_SET_PN( saved_packet );
1888 +/*----------------------------------------------------
1891 + . this makes the board clean up everything that it can
1892 + . and not talk to the outside world. Caused by
1893 + . an 'ifconfig ethX down'
1895 + -----------------------------------------------------*/
1896 +static int smc_close(struct net_device *dev)
1898 + PRINTK2("%s:smc_close\n", dev->name);
1900 + netif_stop_queue(dev);
1902 +#ifdef CONFIG_SYSCTL
1903 + smc_sysctl_unregister(dev);
1904 +#endif /* CONFIG_SYSCTL */
1906 + /* clear everything */
1907 + smc_shutdown( dev->base_addr );
1909 + /* Update the statistics here. */
1913 +/*------------------------------------------------------------
1914 + . Get the current statistics.
1915 + . This may be called with the card open or closed.
1916 + .-------------------------------------------------------------*/
1917 +static struct net_device_stats* smc_query_statistics(struct net_device *dev) {
1918 + struct smc_local *lp = (struct smc_local *)dev->priv;
1920 + PRINTK2("%s:smc_query_statistics\n", dev->name);
1922 + return &lp->stats;
1925 +/*-----------------------------------------------------------
1926 + . smc_set_multicast_list
1928 + . This routine will, depending on the values passed to it,
1929 + . either make it accept multicast packets, go into
1930 + . promiscuous mode ( for TCPDUMP and cousins ) or accept
1931 + . a select set of multicast packets
1933 +static void smc_set_multicast_list(struct net_device *dev)
1935 + unsigned long ioaddr = dev->base_addr;
1937 + PRINTK2("%s:smc_set_multicast_list\n", dev->name);
1939 + SMC_SELECT_BANK(0);
1940 + if ( dev->flags & IFF_PROMISC ) {
1941 + PRINTK2("%s:smc_set_multicast_list:RCR_PRMS\n", dev->name);
1942 + SMC_SET_RCR( SMC_GET_RCR() | RCR_PRMS );
1945 +/* BUG? I never disable promiscuous mode if multicasting was turned on.
1946 + Now, I turn off promiscuous mode, but I don't do anything to multicasting
1947 + when promiscuous mode is turned on.
1950 + /* Here, I am setting this to accept all multicast packets.
1951 + I don't need to zero the multicast table, because the flag is
1952 + checked before the table is
1954 + else if (dev->flags & IFF_ALLMULTI) {
1955 + SMC_SET_RCR( SMC_GET_RCR() | RCR_ALMUL );
1956 + PRINTK2("%s:smc_set_multicast_list:RCR_ALMUL\n", dev->name);
1959 + /* We just get all multicast packets even if we only want them
1960 + . from one source. This will be changed at some future
1962 + else if (dev->mc_count ) {
1963 + /* support hardware multicasting */
1965 + /* be sure I get rid of flags I might have set */
1966 + SMC_SET_RCR( SMC_GET_RCR() & ~(RCR_PRMS | RCR_ALMUL) );
1967 + /* NOTE: this has to set the bank, so make sure it is the
1968 + last thing called. The bank is set to zero at the top */
1969 + smc_setmulticast( ioaddr, dev->mc_count, dev->mc_list );
1971 + PRINTK2("%s:smc_set_multicast_list:~(RCR_PRMS|RCR_ALMUL)\n",
1973 + SMC_SET_RCR( SMC_GET_RCR() & ~(RCR_PRMS | RCR_ALMUL) );
1976 + since I'm disabling all multicast entirely, I need to
1977 + clear the multicast list
1979 + SMC_SELECT_BANK( 3 );
1980 + SMC_CLEAR_MCAST();
1984 +/*------------------------------------------------------------
1985 + . Cleanup when module is removed with rmmod
1986 + .-------------------------------------------------------------*/
1987 +static void __exit smc_cleanup(void)
1989 + /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
1990 + unregister_netdev(global_dev);
1992 + free_irq(global_dev->irq, global_dev);
1993 + release_region(global_dev->base_addr, SMC_IO_EXTENT);
1996 + iounmap((void *)global_dev->base_addr);
1999 + kfree(global_dev);
2000 + global_dev = NULL;
2003 +module_init(smc_init);
2004 +module_exit(smc_cleanup);
2007 +#ifdef CONFIG_SYSCTL
2008 +/*------------------------------------------------------------
2009 + . Modify a bit in the LAN91C111 register set
2010 + .-------------------------------------------------------------*/
2011 +static word smc_modify_regbit(int bank, unsigned long ioaddr, int reg,
2012 + unsigned int bit, int val)
2016 + SMC_SELECT_BANK( bank );
2018 + regval = SMC_inw( ioaddr+reg );
2024 + SMC_outw( regval, ioaddr );
2029 +/*------------------------------------------------------------
2030 + . Retrieve a bit in the LAN91C111 register set
2031 + .-------------------------------------------------------------*/
2032 +static int smc_get_regbit(int bank, unsigned long ioaddr,
2033 + int reg, unsigned int bit)
2035 + SMC_SELECT_BANK( bank );
2036 + if ( SMC_inw( ioaddr+reg ) & bit)
2043 +/*------------------------------------------------------------
2044 + . Modify a LAN91C111 register (word access only)
2045 + .-------------------------------------------------------------*/
2046 +static void smc_modify_reg(int bank, unsigned long ioaddr,
2047 + int reg, word val)
2049 + SMC_SELECT_BANK( bank );
2050 + SMC_outw( val, ioaddr+reg );
2054 +/*------------------------------------------------------------
2055 + . Retrieve a LAN91C111 register (word access only)
2056 + .-------------------------------------------------------------*/
2057 +static int smc_get_reg(int bank, unsigned long ioaddr,
2060 + SMC_SELECT_BANK( bank );
2061 + return(SMC_inw( ioaddr+reg ));
2065 +static const char smc_info_string[] =
2067 +"info Provides this information blurb\n"
2068 +"swver Prints the software version information of this driver\n"
2069 +"autoneg Auto-negotiate Mode = 1\n"
2070 +"rspeed Requested Speed, 100=100Mbps, 10=10Mpbs\n"
2071 +"rfduplx Requested Full Duplex Operation\n"
2072 +"aspeed Actual Speed, 100=100Mbps, 10=10Mpbs\n"
2073 +"afduplx Actual Full Duplex Operation\n"
2074 +"lnkfail PHY Link Failure when 1\n"
2075 +"miiop External MII when 1, Internal PHY when 0\n"
2076 +"swfdup Switched Full Duplex Mode (allowed only in MII operation)\n"
2077 +"ephloop EPH Block Loopback\n"
2078 +"forcol Force a collision\n"
2079 +"filtcar Filter leading edge of carrier sense for 12 bit times\n"
2080 +"freemem Free buffer memory in bytes\n"
2081 +"totmem Total buffer memory in bytes\n"
2082 +"leda Output of LED-A (green)\n"
2083 +"ledb Output of LED-B (yellow)\n"
2084 +"chiprev Revision ID of the LAN91C111 chip\n"
2087 +/*------------------------------------------------------------
2088 + . Sysctl handler for all integer parameters
2089 + .-------------------------------------------------------------*/
2090 +static int smc_sysctl_handler(ctl_table *ctl, int write, struct file * filp,
2091 + void *buffer, size_t *lenp)
2093 + struct net_device *dev = (struct net_device*)ctl->extra1;
2094 + struct smc_local *lp = (struct smc_local *)ctl->extra2;
2095 + unsigned long ioaddr = dev->base_addr;
2096 + int *valp = ctl->data;
2100 + // Update parameters from the real registers
2101 + switch (ctl->ctl_name)
2103 + case CTL_SMC_FORCOL:
2104 + *valp = smc_get_regbit(0, ioaddr, TCR_REG, TCR_FORCOL);
2107 + case CTL_SMC_FREEMEM:
2108 + *valp = ( (word)smc_get_reg(0, ioaddr, MIR_REG) >> 8 )
2109 + * LAN91C111_MEMORY_MULTIPLIER;
2113 + case CTL_SMC_TOTMEM:
2114 + *valp = ( smc_get_reg(0, ioaddr, MIR_REG) & (word)0x00ff )
2115 + * LAN91C111_MEMORY_MULTIPLIER;
2118 + case CTL_SMC_CHIPREV:
2119 + *valp = smc_get_reg(3, ioaddr, REV_REG);
2122 + case CTL_SMC_AFDUPLX:
2123 + *valp = (lp->lastPhy18 & PHY_INT_DPLXDET) ? 1 : 0;
2126 + case CTL_SMC_ASPEED:
2127 + *valp = (lp->lastPhy18 & PHY_INT_SPDDET) ? 100 : 10;
2130 + case CTL_SMC_LNKFAIL:
2131 + *valp = (lp->lastPhy18 & PHY_INT_LNKFAIL) ? 1 : 0;
2134 + case CTL_SMC_LEDA:
2135 + *valp = (lp->rpc_cur_mode >> RPC_LSXA_SHFT) & (word)0x0007;
2138 + case CTL_SMC_LEDB:
2139 + *valp = (lp->rpc_cur_mode >> RPC_LSXB_SHFT) & (word)0x0007;
2142 + case CTL_SMC_MIIOP:
2143 + *valp = smc_get_regbit(1, ioaddr, CONFIG_REG, CONFIG_EXT_PHY);
2147 + case CTL_SMC_REG_BSR: // Bank Select
2148 + *valp = smc_get_reg(0, ioaddr, BSR_REG);
2151 + case CTL_SMC_REG_TCR: // Transmit Control
2152 + *valp = smc_get_reg(0, ioaddr, TCR_REG);
2155 + case CTL_SMC_REG_ESR: // EPH Status
2156 + *valp = smc_get_reg(0, ioaddr, EPH_STATUS_REG);
2159 + case CTL_SMC_REG_RCR: // Receive Control
2160 + *valp = smc_get_reg(0, ioaddr, RCR_REG);
2163 + case CTL_SMC_REG_CTRR: // Counter
2164 + *valp = smc_get_reg(0, ioaddr, COUNTER_REG);
2167 + case CTL_SMC_REG_MIR: // Memory Information
2168 + *valp = smc_get_reg(0, ioaddr, MIR_REG);
2171 + case CTL_SMC_REG_RPCR: // Receive/Phy Control
2172 + *valp = smc_get_reg(0, ioaddr, RPC_REG);
2175 + case CTL_SMC_REG_CFGR: // Configuration
2176 + *valp = smc_get_reg(1, ioaddr, CONFIG_REG);
2179 + case CTL_SMC_REG_BAR: // Base Address
2180 + *valp = smc_get_reg(1, ioaddr, BASE_REG);
2183 + case CTL_SMC_REG_IAR0: // Individual Address
2184 + *valp = smc_get_reg(1, ioaddr, ADDR0_REG);
2187 + case CTL_SMC_REG_IAR1: // Individual Address
2188 + *valp = smc_get_reg(1, ioaddr, ADDR1_REG);
2191 + case CTL_SMC_REG_IAR2: // Individual Address
2192 + *valp = smc_get_reg(1, ioaddr, ADDR2_REG);
2195 + case CTL_SMC_REG_GPR: // General Purpose
2196 + *valp = smc_get_reg(1, ioaddr, GP_REG);
2199 + case CTL_SMC_REG_CTLR: // Control
2200 + *valp = smc_get_reg(1, ioaddr, CTL_REG);
2203 + case CTL_SMC_REG_MCR: // MMU Command
2204 + *valp = smc_get_reg(2, ioaddr, MMU_CMD_REG);
2207 + case CTL_SMC_REG_PNR: // Packet Number
2208 + *valp = smc_get_reg(2, ioaddr, PN_REG);
2211 + case CTL_SMC_REG_FPR: // Allocation Result/FIFO Ports
2212 + *valp = smc_get_reg(2, ioaddr, RXFIFO_REG);
2215 + case CTL_SMC_REG_PTR: // Pointer
2216 + *valp = smc_get_reg(2, ioaddr, PTR_REG);
2219 + case CTL_SMC_REG_DR: // Data
2220 + *valp = smc_get_reg(2, ioaddr, DATA_REG);
2223 + case CTL_SMC_REG_ISR: // Interrupt Status/Mask
2224 + *valp = smc_get_reg(2, ioaddr, INT_REG);
2227 + case CTL_SMC_REG_MTR1: // Multicast Table Entry 1
2228 + *valp = smc_get_reg(3, ioaddr, MCAST_REG1);
2231 + case CTL_SMC_REG_MTR2: // Multicast Table Entry 2
2232 + *valp = smc_get_reg(3, ioaddr, MCAST_REG2);
2235 + case CTL_SMC_REG_MTR3: // Multicast Table Entry 3
2236 + *valp = smc_get_reg(3, ioaddr, MCAST_REG3);
2239 + case CTL_SMC_REG_MTR4: // Multicast Table Entry 4
2240 + *valp = smc_get_reg(3, ioaddr, MCAST_REG4);
2243 + case CTL_SMC_REG_MIIR: // Management Interface
2244 + *valp = smc_get_reg(3, ioaddr, MII_REG);
2247 + case CTL_SMC_REG_REVR: // Revision
2248 + *valp = smc_get_reg(3, ioaddr, REV_REG);
2251 + case CTL_SMC_REG_ERCVR: // Early RCV
2252 + *valp = smc_get_reg(3, ioaddr, ERCV_REG);
2255 + case CTL_SMC_REG_EXTR: // External
2256 + *valp = smc_get_reg(7, ioaddr, EXT_REG);
2259 + case CTL_SMC_PHY_CTRL:
2260 + *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2264 + case CTL_SMC_PHY_STAT:
2265 + *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2269 + case CTL_SMC_PHY_ID1:
2270 + *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2274 + case CTL_SMC_PHY_ID2:
2275 + *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2279 + case CTL_SMC_PHY_ADC:
2280 + *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2284 + case CTL_SMC_PHY_REMC:
2285 + *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2289 + case CTL_SMC_PHY_CFG1:
2290 + *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2294 + case CTL_SMC_PHY_CFG2:
2295 + *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2299 + case CTL_SMC_PHY_INT:
2300 + *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2304 + case CTL_SMC_PHY_MASK:
2305 + *valp = smc_read_phy_register(ioaddr, lp->phyaddr,
2309 +#endif // SMC_DEBUG > 1
2312 + // Just ignore unsupported parameters
2319 + // Perform the generic integer operation
2320 + if ((ret = proc_dointvec(ctl, write, filp, buffer, lenp)) != 0)
2323 + // Write changes out to the registers
2324 + if (write && *valp != val) {
2327 + switch (ctl->ctl_name) {
2329 + case CTL_SMC_SWFDUP:
2331 + lp->tcr_cur_mode |= TCR_SWFDUP;
2333 + lp->tcr_cur_mode &= ~TCR_SWFDUP;
2335 + smc_modify_regbit(0, ioaddr, TCR_REG, TCR_SWFDUP, val);
2338 + case CTL_SMC_EPHLOOP:
2340 + lp->tcr_cur_mode |= TCR_EPH_LOOP;
2342 + lp->tcr_cur_mode &= ~TCR_EPH_LOOP;
2344 + smc_modify_regbit(0, ioaddr, TCR_REG, TCR_EPH_LOOP, val);
2347 + case CTL_SMC_FORCOL:
2349 + lp->tcr_cur_mode |= TCR_FORCOL;
2351 + lp->tcr_cur_mode &= ~TCR_FORCOL;
2353 + // Update the EPH block
2354 + smc_modify_regbit(0, ioaddr, TCR_REG, TCR_FORCOL, val);
2357 + case CTL_SMC_FILTCAR:
2359 + lp->rcr_cur_mode |= RCR_FILT_CAR;
2361 + lp->rcr_cur_mode &= ~RCR_FILT_CAR;
2363 + // Update the EPH block
2364 + smc_modify_regbit(0, ioaddr, RCR_REG, RCR_FILT_CAR, val);
2367 + case CTL_SMC_RFDUPLX:
2368 + // Disallow changes if in auto-negotiation mode
2369 + if (lp->ctl_autoneg)
2373 + lp->rpc_cur_mode |= RPC_DPLX;
2375 + lp->rpc_cur_mode &= ~RPC_DPLX;
2377 + // Reconfigure the PHY
2378 + smc_phy_configure(dev);
2382 + case CTL_SMC_RSPEED:
2383 + // Disallow changes if in auto-negotiation mode
2384 + if (lp->ctl_autoneg)
2388 + lp->rpc_cur_mode |= RPC_SPEED;
2390 + lp->rpc_cur_mode &= ~RPC_SPEED;
2392 + // Reconfigure the PHY
2393 + smc_phy_configure(dev);
2397 + case CTL_SMC_AUTONEG:
2399 + lp->rpc_cur_mode |= RPC_ANEG;
2401 + lp->rpc_cur_mode &= ~RPC_ANEG;
2403 + // Reconfigure the PHY
2404 + smc_phy_configure(dev);
2408 + case CTL_SMC_LEDA:
2409 + val &= 0x07; // Restrict to 3 ls bits
2410 + lp->rpc_cur_mode &= ~(word)(0x07<<RPC_LSXA_SHFT);
2411 + lp->rpc_cur_mode |= (word)(val<<RPC_LSXA_SHFT);
2413 + // Update the Internal PHY block
2414 + smc_modify_reg(0, ioaddr, RPC_REG, lp->rpc_cur_mode);
2417 + case CTL_SMC_LEDB:
2418 + val &= 0x07; // Restrict to 3 ls bits
2419 + lp->rpc_cur_mode &= ~(word)(0x07<<RPC_LSXB_SHFT);
2420 + lp->rpc_cur_mode |= (word)(val<<RPC_LSXB_SHFT);
2422 + // Update the Internal PHY block
2423 + smc_modify_reg(0, ioaddr, RPC_REG, lp->rpc_cur_mode);
2426 + case CTL_SMC_MIIOP:
2427 + // Update the Internal PHY block
2428 + smc_modify_regbit(1, ioaddr, CONFIG_REG,
2429 + CONFIG_EXT_PHY, val);
2433 + case CTL_SMC_REG_BSR: // Bank Select
2434 + smc_modify_reg(0, ioaddr, BSR_REG, val);
2437 + case CTL_SMC_REG_TCR: // Transmit Control
2438 + smc_modify_reg(0, ioaddr, TCR_REG, val);
2441 + case CTL_SMC_REG_ESR: // EPH Status
2442 + smc_modify_reg(0, ioaddr, EPH_STATUS_REG, val);
2445 + case CTL_SMC_REG_RCR: // Receive Control
2446 + smc_modify_reg(0, ioaddr, RCR_REG, val);
2449 + case CTL_SMC_REG_CTRR: // Counter
2450 + smc_modify_reg(0, ioaddr, COUNTER_REG, val);
2453 + case CTL_SMC_REG_MIR: // Memory Information
2454 + smc_modify_reg(0, ioaddr, MIR_REG, val);
2457 + case CTL_SMC_REG_RPCR: // Receive/Phy Control
2458 + smc_modify_reg(0, ioaddr, RPC_REG, val);
2461 + case CTL_SMC_REG_CFGR: // Configuration
2462 + smc_modify_reg(1, ioaddr, CONFIG_REG, val);
2465 + case CTL_SMC_REG_BAR: // Base Address
2466 + smc_modify_reg(1, ioaddr, BASE_REG, val);
2469 + case CTL_SMC_REG_IAR0: // Individual Address
2470 + smc_modify_reg(1, ioaddr, ADDR0_REG, val);
2473 + case CTL_SMC_REG_IAR1: // Individual Address
2474 + smc_modify_reg(1, ioaddr, ADDR1_REG, val);
2477 + case CTL_SMC_REG_IAR2: // Individual Address
2478 + smc_modify_reg(1, ioaddr, ADDR2_REG, val);
2481 + case CTL_SMC_REG_GPR: // General Purpose
2482 + smc_modify_reg(1, ioaddr, GP_REG, val);
2485 + case CTL_SMC_REG_CTLR: // Control
2486 + smc_modify_reg(1, ioaddr, CTL_REG, val);
2489 + case CTL_SMC_REG_MCR: // MMU Command
2490 + smc_modify_reg(2, ioaddr, MMU_CMD_REG, val);
2493 + case CTL_SMC_REG_PNR: // Packet Number
2494 + smc_modify_reg(2, ioaddr, PN_REG, val);
2497 + case CTL_SMC_REG_FPR: // Allocation Result/FIFO Ports
2498 + smc_modify_reg(2, ioaddr, RXFIFO_REG, val);
2501 + case CTL_SMC_REG_PTR: // Pointer
2502 + smc_modify_reg(2, ioaddr, PTR_REG, val);
2505 + case CTL_SMC_REG_DR: // Data
2506 + smc_modify_reg(2, ioaddr, DATA_REG, val);
2509 + case CTL_SMC_REG_ISR: // Interrupt Status/Mask
2510 + smc_modify_reg(2, ioaddr, INT_REG, val);
2513 + case CTL_SMC_REG_MTR1: // Multicast Table Entry 1
2514 + smc_modify_reg(3, ioaddr, MCAST_REG1, val);
2517 + case CTL_SMC_REG_MTR2: // Multicast Table Entry 2
2518 + smc_modify_reg(3, ioaddr, MCAST_REG2, val);
2521 + case CTL_SMC_REG_MTR3: // Multicast Table Entry 3
2522 + smc_modify_reg(3, ioaddr, MCAST_REG3, val);
2525 + case CTL_SMC_REG_MTR4: // Multicast Table Entry 4
2526 + smc_modify_reg(3, ioaddr, MCAST_REG4, val);
2529 + case CTL_SMC_REG_MIIR: // Management Interface
2530 + smc_modify_reg(3, ioaddr, MII_REG, val);
2533 + case CTL_SMC_REG_REVR: // Revision
2534 + smc_modify_reg(3, ioaddr, REV_REG, val);
2537 + case CTL_SMC_REG_ERCVR: // Early RCV
2538 + smc_modify_reg(3, ioaddr, ERCV_REG, val);
2541 + case CTL_SMC_REG_EXTR: // External
2542 + smc_modify_reg(7, ioaddr, EXT_REG, val);
2545 + case CTL_SMC_PHY_CTRL:
2546 + smc_write_phy_register(ioaddr, lp->phyaddr,
2547 + PHY_CNTL_REG, val);
2550 + case CTL_SMC_PHY_STAT:
2551 + smc_write_phy_register(ioaddr, lp->phyaddr,
2552 + PHY_STAT_REG, val);
2555 + case CTL_SMC_PHY_ID1:
2556 + smc_write_phy_register(ioaddr, lp->phyaddr,
2557 + PHY_ID1_REG, val);
2560 + case CTL_SMC_PHY_ID2:
2561 + smc_write_phy_register(ioaddr, lp->phyaddr,
2562 + PHY_ID2_REG, val);
2565 + case CTL_SMC_PHY_ADC:
2566 + smc_write_phy_register(ioaddr, lp->phyaddr,
2570 + case CTL_SMC_PHY_REMC:
2571 + smc_write_phy_register(ioaddr, lp->phyaddr,
2572 + PHY_RMT_REG, val);
2575 + case CTL_SMC_PHY_CFG1:
2576 + smc_write_phy_register(ioaddr, lp->phyaddr,
2577 + PHY_CFG1_REG, val);
2580 + case CTL_SMC_PHY_CFG2:
2581 + smc_write_phy_register(ioaddr, lp->phyaddr,
2582 + PHY_CFG2_REG, val);
2585 + case CTL_SMC_PHY_INT:
2586 + smc_write_phy_register(ioaddr, lp->phyaddr,
2587 + PHY_INT_REG, val);
2590 + case CTL_SMC_PHY_MASK:
2591 + smc_write_phy_register(ioaddr, lp->phyaddr,
2592 + PHY_MASK_REG, val);
2595 +#endif // SMC_DEBUG > 1
2598 + // Just ignore unsupported parameters
2610 + * This is called as the fill_inode function when an inode
2611 + * is going into (fill = 1) or out of service (fill = 0).
2612 + * We use it here to manage the module use counts.
2614 + * Note: only the top-level directory needs to do this; if
2615 + * a lower level is referenced, the parent will be as well.
2617 +static void smc_procfs_modcount(struct inode *inode, int fill)
2620 + MOD_INC_USE_COUNT;
2622 + MOD_DEC_USE_COUNT;
2626 +/*------------------------------------------------------------
2627 + . Sysctl registration function for all parameters (files)
2628 + .-------------------------------------------------------------*/
2629 +static void smc_sysctl_register(struct net_device *dev)
2631 + struct smc_local *lp = (struct smc_local *)dev->priv;
2632 + static int ctl_name = CTL_SMC;
2636 + // Make sure the ctl_tables start out as all zeros
2637 + memset(lp->root_table, 0, sizeof lp->root_table);
2638 + memset(lp->eth_table, 0, sizeof lp->eth_table);
2639 + memset(lp->param_table, 0, sizeof lp->param_table);
2641 + // Initialize the root table
2642 + ct = lp->root_table;
2643 + ct->ctl_name = CTL_DEV;
2644 + ct->procname = "dev";
2647 + ct->child = lp->eth_table;
2648 + // remaining fields are zero
2650 + // Initialize the ethX table (this device's table)
2651 + ct = lp->eth_table;
2652 + ct->ctl_name = ctl_name++; // Must be unique
2653 + ct->procname = dev->name;
2656 + ct->child = lp->param_table;
2657 + // remaining fields are zero
2659 + // Initialize the parameter (files) table
2660 + // Make sure the last entry remains null
2661 + ct = lp->param_table;
2662 + for (i = 0; i < (CTL_SMC_LAST_ENTRY-1); ++i) {
2663 + // Initialize fields common to all table entries
2664 + ct[i].proc_handler = smc_sysctl_handler;
2665 + ct[i].extra1 = (void*)dev; // Save our device pointer
2666 + ct[i].extra2 = (void*)lp; // Save our smc_local data pointer
2669 + // INFO - this is our only string parameter
2671 + ct[i].proc_handler = proc_dostring; // use default handler
2672 + ct[i].ctl_name = CTL_SMC_INFO;
2673 + ct[i].procname = "info";
2674 + ct[i].data = (void*)smc_info_string;
2675 + ct[i].maxlen = sizeof smc_info_string;
2676 + ct[i].mode = 0444; // Read only
2680 + ct[i].proc_handler = proc_dostring; // use default handler
2681 + ct[i].ctl_name = CTL_SMC_SWVER;
2682 + ct[i].procname = "swver";
2683 + ct[i].data = (void*)version;
2684 + ct[i].maxlen = sizeof version;
2685 + ct[i].mode = 0444; // Read only
2689 + ct[i].ctl_name = CTL_SMC_SWFDUP;
2690 + ct[i].procname = "swfdup";
2691 + ct[i].data = (void*)&(lp->ctl_swfdup);
2692 + ct[i].maxlen = sizeof lp->ctl_swfdup;
2693 + ct[i].mode = 0644; // Read by all, write by root
2697 + ct[i].ctl_name = CTL_SMC_EPHLOOP;
2698 + ct[i].procname = "ephloop";
2699 + ct[i].data = (void*)&(lp->ctl_ephloop);
2700 + ct[i].maxlen = sizeof lp->ctl_ephloop;
2701 + ct[i].mode = 0644; // Read by all, write by root
2705 + ct[i].ctl_name = CTL_SMC_MIIOP;
2706 + ct[i].procname = "miiop";
2707 + ct[i].data = (void*)&(lp->ctl_miiop);
2708 + ct[i].maxlen = sizeof lp->ctl_miiop;
2709 + ct[i].mode = 0644; // Read by all, write by root
2713 + ct[i].ctl_name = CTL_SMC_AUTONEG;
2714 + ct[i].procname = "autoneg";
2715 + ct[i].data = (void*)&(lp->ctl_autoneg);
2716 + ct[i].maxlen = sizeof lp->ctl_autoneg;
2717 + ct[i].mode = 0644; // Read by all, write by root
2721 + ct[i].ctl_name = CTL_SMC_RFDUPLX;
2722 + ct[i].procname = "rfduplx";
2723 + ct[i].data = (void*)&(lp->ctl_rfduplx);
2724 + ct[i].maxlen = sizeof lp->ctl_rfduplx;
2725 + ct[i].mode = 0644; // Read by all, write by root
2729 + ct[i].ctl_name = CTL_SMC_RSPEED;
2730 + ct[i].procname = "rspeed";
2731 + ct[i].data = (void*)&(lp->ctl_rspeed);
2732 + ct[i].maxlen = sizeof lp->ctl_rspeed;
2733 + ct[i].mode = 0644; // Read by all, write by root
2737 + ct[i].ctl_name = CTL_SMC_AFDUPLX;
2738 + ct[i].procname = "afduplx";
2739 + ct[i].data = (void*)&(lp->ctl_afduplx);
2740 + ct[i].maxlen = sizeof lp->ctl_afduplx;
2741 + ct[i].mode = 0444; // Read only
2745 + ct[i].ctl_name = CTL_SMC_ASPEED;
2746 + ct[i].procname = "aspeed";
2747 + ct[i].data = (void*)&(lp->ctl_aspeed);
2748 + ct[i].maxlen = sizeof lp->ctl_aspeed;
2749 + ct[i].mode = 0444; // Read only
2753 + ct[i].ctl_name = CTL_SMC_LNKFAIL;
2754 + ct[i].procname = "lnkfail";
2755 + ct[i].data = (void*)&(lp->ctl_lnkfail);
2756 + ct[i].maxlen = sizeof lp->ctl_lnkfail;
2757 + ct[i].mode = 0444; // Read only
2761 + ct[i].ctl_name = CTL_SMC_FORCOL;
2762 + ct[i].procname = "forcol";
2763 + ct[i].data = (void*)&(lp->ctl_forcol);
2764 + ct[i].maxlen = sizeof lp->ctl_forcol;
2765 + ct[i].mode = 0644; // Read by all, write by root
2769 + ct[i].ctl_name = CTL_SMC_FILTCAR;
2770 + ct[i].procname = "filtcar";
2771 + ct[i].data = (void*)&(lp->ctl_filtcar);
2772 + ct[i].maxlen = sizeof lp->ctl_filtcar;
2773 + ct[i].mode = 0644; // Read by all, write by root
2777 + ct[i].ctl_name = CTL_SMC_FREEMEM;
2778 + ct[i].procname = "freemem";
2779 + ct[i].data = (void*)&(lp->ctl_freemem);
2780 + ct[i].maxlen = sizeof lp->ctl_freemem;
2781 + ct[i].mode = 0444; // Read only
2785 + ct[i].ctl_name = CTL_SMC_TOTMEM;
2786 + ct[i].procname = "totmem";
2787 + ct[i].data = (void*)&(lp->ctl_totmem);
2788 + ct[i].maxlen = sizeof lp->ctl_totmem;
2789 + ct[i].mode = 0444; // Read only
2793 + ct[i].ctl_name = CTL_SMC_LEDA;
2794 + ct[i].procname = "leda";
2795 + ct[i].data = (void*)&(lp->ctl_leda);
2796 + ct[i].maxlen = sizeof lp->ctl_leda;
2797 + ct[i].mode = 0644; // Read by all, write by root
2801 + ct[i].ctl_name = CTL_SMC_LEDB;
2802 + ct[i].procname = "ledb";
2803 + ct[i].data = (void*)&(lp->ctl_ledb);
2804 + ct[i].maxlen = sizeof lp->ctl_ledb;
2805 + ct[i].mode = 0644; // Read by all, write by root
2809 + ct[i].ctl_name = CTL_SMC_CHIPREV;
2810 + ct[i].procname = "chiprev";
2811 + ct[i].data = (void*)&(lp->ctl_chiprev);
2812 + ct[i].maxlen = sizeof lp->ctl_chiprev;
2813 + ct[i].mode = 0444; // Read only
2818 + ct[i].ctl_name = CTL_SMC_REG_BSR;
2819 + ct[i].procname = "reg_bsr";
2820 + ct[i].data = (void*)&(lp->ctl_reg_bsr);
2821 + ct[i].maxlen = sizeof lp->ctl_reg_bsr;
2822 + ct[i].mode = 0644; // Read by all, write by root
2826 + ct[i].ctl_name = CTL_SMC_REG_TCR;
2827 + ct[i].procname = "reg_tcr";
2828 + ct[i].data = (void*)&(lp->ctl_reg_tcr);
2829 + ct[i].maxlen = sizeof lp->ctl_reg_tcr;
2830 + ct[i].mode = 0644; // Read by all, write by root
2834 + ct[i].ctl_name = CTL_SMC_REG_ESR;
2835 + ct[i].procname = "reg_esr";
2836 + ct[i].data = (void*)&(lp->ctl_reg_esr);
2837 + ct[i].maxlen = sizeof lp->ctl_reg_esr;
2838 + ct[i].mode = 0644; // Read by all, write by root
2842 + ct[i].ctl_name = CTL_SMC_REG_RCR;
2843 + ct[i].procname = "reg_rcr";
2844 + ct[i].data = (void*)&(lp->ctl_reg_rcr);
2845 + ct[i].maxlen = sizeof lp->ctl_reg_rcr;
2846 + ct[i].mode = 0644; // Read by all, write by root
2850 + ct[i].ctl_name = CTL_SMC_REG_CTRR;
2851 + ct[i].procname = "reg_ctrr";
2852 + ct[i].data = (void*)&(lp->ctl_reg_ctrr);
2853 + ct[i].maxlen = sizeof lp->ctl_reg_ctrr;
2854 + ct[i].mode = 0644; // Read by all, write by root
2858 + ct[i].ctl_name = CTL_SMC_REG_MIR;
2859 + ct[i].procname = "reg_mir";
2860 + ct[i].data = (void*)&(lp->ctl_reg_mir);
2861 + ct[i].maxlen = sizeof lp->ctl_reg_mir;
2862 + ct[i].mode = 0644; // Read by all, write by root
2866 + ct[i].ctl_name = CTL_SMC_REG_RPCR;
2867 + ct[i].procname = "reg_rpcr";
2868 + ct[i].data = (void*)&(lp->ctl_reg_rpcr);
2869 + ct[i].maxlen = sizeof lp->ctl_reg_rpcr;
2870 + ct[i].mode = 0644; // Read by all, write by root
2874 + ct[i].ctl_name = CTL_SMC_REG_CFGR;
2875 + ct[i].procname = "reg_cfgr";
2876 + ct[i].data = (void*)&(lp->ctl_reg_cfgr);
2877 + ct[i].maxlen = sizeof lp->ctl_reg_cfgr;
2878 + ct[i].mode = 0644; // Read by all, write by root
2882 + ct[i].ctl_name = CTL_SMC_REG_BAR;
2883 + ct[i].procname = "reg_bar";
2884 + ct[i].data = (void*)&(lp->ctl_reg_bar);
2885 + ct[i].maxlen = sizeof lp->ctl_reg_bar;
2886 + ct[i].mode = 0644; // Read by all, write by root
2890 + ct[i].ctl_name = CTL_SMC_REG_IAR0;
2891 + ct[i].procname = "reg_iar0";
2892 + ct[i].data = (void*)&(lp->ctl_reg_iar0);
2893 + ct[i].maxlen = sizeof lp->ctl_reg_iar0;
2894 + ct[i].mode = 0644; // Read by all, write by root
2898 + ct[i].ctl_name = CTL_SMC_REG_IAR1;
2899 + ct[i].procname = "reg_iar1";
2900 + ct[i].data = (void*)&(lp->ctl_reg_iar1);
2901 + ct[i].maxlen = sizeof lp->ctl_reg_iar1;
2902 + ct[i].mode = 0644; // Read by all, write by root
2906 + ct[i].ctl_name = CTL_SMC_REG_IAR2;
2907 + ct[i].procname = "reg_iar2";
2908 + ct[i].data = (void*)&(lp->ctl_reg_iar2);
2909 + ct[i].maxlen = sizeof lp->ctl_reg_iar2;
2910 + ct[i].mode = 0644; // Read by all, write by root
2914 + ct[i].ctl_name = CTL_SMC_REG_GPR;
2915 + ct[i].procname = "reg_gpr";
2916 + ct[i].data = (void*)&(lp->ctl_reg_gpr);
2917 + ct[i].maxlen = sizeof lp->ctl_reg_gpr;
2918 + ct[i].mode = 0644; // Read by all, write by root
2922 + ct[i].ctl_name = CTL_SMC_REG_CTLR;
2923 + ct[i].procname = "reg_ctlr";
2924 + ct[i].data = (void*)&(lp->ctl_reg_ctlr);
2925 + ct[i].maxlen = sizeof lp->ctl_reg_ctlr;
2926 + ct[i].mode = 0644; // Read by all, write by root
2930 + ct[i].ctl_name = CTL_SMC_REG_MCR;
2931 + ct[i].procname = "reg_mcr";
2932 + ct[i].data = (void*)&(lp->ctl_reg_mcr);
2933 + ct[i].maxlen = sizeof lp->ctl_reg_mcr;
2934 + ct[i].mode = 0644; // Read by all, write by root
2938 + ct[i].ctl_name = CTL_SMC_REG_PNR;
2939 + ct[i].procname = "reg_pnr";
2940 + ct[i].data = (void*)&(lp->ctl_reg_pnr);
2941 + ct[i].maxlen = sizeof lp->ctl_reg_pnr;
2942 + ct[i].mode = 0644; // Read by all, write by root
2946 + ct[i].ctl_name = CTL_SMC_REG_FPR;
2947 + ct[i].procname = "reg_fpr";
2948 + ct[i].data = (void*)&(lp->ctl_reg_fpr);
2949 + ct[i].maxlen = sizeof lp->ctl_reg_fpr;
2950 + ct[i].mode = 0644; // Read by all, write by root
2954 + ct[i].ctl_name = CTL_SMC_REG_PTR;
2955 + ct[i].procname = "reg_ptr";
2956 + ct[i].data = (void*)&(lp->ctl_reg_ptr);
2957 + ct[i].maxlen = sizeof lp->ctl_reg_ptr;
2958 + ct[i].mode = 0644; // Read by all, write by root
2962 + ct[i].ctl_name = CTL_SMC_REG_DR;
2963 + ct[i].procname = "reg_dr";
2964 + ct[i].data = (void*)&(lp->ctl_reg_dr);
2965 + ct[i].maxlen = sizeof lp->ctl_reg_dr;
2966 + ct[i].mode = 0644; // Read by all, write by root
2970 + ct[i].ctl_name = CTL_SMC_REG_ISR;
2971 + ct[i].procname = "reg_isr";
2972 + ct[i].data = (void*)&(lp->ctl_reg_isr);
2973 + ct[i].maxlen = sizeof lp->ctl_reg_isr;
2974 + ct[i].mode = 0644; // Read by all, write by root
2978 + ct[i].ctl_name = CTL_SMC_REG_MTR1;
2979 + ct[i].procname = "reg_mtr1";
2980 + ct[i].data = (void*)&(lp->ctl_reg_mtr1);
2981 + ct[i].maxlen = sizeof lp->ctl_reg_mtr1;
2982 + ct[i].mode = 0644; // Read by all, write by root
2986 + ct[i].ctl_name = CTL_SMC_REG_MTR2;
2987 + ct[i].procname = "reg_mtr2";
2988 + ct[i].data = (void*)&(lp->ctl_reg_mtr2);
2989 + ct[i].maxlen = sizeof lp->ctl_reg_mtr2;
2990 + ct[i].mode = 0644; // Read by all, write by root
2994 + ct[i].ctl_name = CTL_SMC_REG_MTR3;
2995 + ct[i].procname = "reg_mtr3";
2996 + ct[i].data = (void*)&(lp->ctl_reg_mtr3);
2997 + ct[i].maxlen = sizeof lp->ctl_reg_mtr3;
2998 + ct[i].mode = 0644; // Read by all, write by root
3002 + ct[i].ctl_name = CTL_SMC_REG_MTR4;
3003 + ct[i].procname = "reg_mtr4";
3004 + ct[i].data = (void*)&(lp->ctl_reg_mtr4);
3005 + ct[i].maxlen = sizeof lp->ctl_reg_mtr4;
3006 + ct[i].mode = 0644; // Read by all, write by root
3010 + ct[i].ctl_name = CTL_SMC_REG_MIIR;
3011 + ct[i].procname = "reg_miir";
3012 + ct[i].data = (void*)&(lp->ctl_reg_miir);
3013 + ct[i].maxlen = sizeof lp->ctl_reg_miir;
3014 + ct[i].mode = 0644; // Read by all, write by root
3018 + ct[i].ctl_name = CTL_SMC_REG_REVR;
3019 + ct[i].procname = "reg_revr";
3020 + ct[i].data = (void*)&(lp->ctl_reg_revr);
3021 + ct[i].maxlen = sizeof lp->ctl_reg_revr;
3022 + ct[i].mode = 0644; // Read by all, write by root
3026 + ct[i].ctl_name = CTL_SMC_REG_ERCVR;
3027 + ct[i].procname = "reg_ercvr";
3028 + ct[i].data = (void*)&(lp->ctl_reg_ercvr);
3029 + ct[i].maxlen = sizeof lp->ctl_reg_ercvr;
3030 + ct[i].mode = 0644; // Read by all, write by root
3034 + ct[i].ctl_name = CTL_SMC_REG_EXTR;
3035 + ct[i].procname = "reg_extr";
3036 + ct[i].data = (void*)&(lp->ctl_reg_extr);
3037 + ct[i].maxlen = sizeof lp->ctl_reg_extr;
3038 + ct[i].mode = 0644; // Read by all, write by root
3042 + ct[i].ctl_name = CTL_SMC_PHY_CTRL;
3043 + ct[i].procname = "phy_ctrl";
3044 + ct[i].data = (void*)&(lp->ctl_phy_ctrl);
3045 + ct[i].maxlen = sizeof lp->ctl_phy_ctrl;
3046 + ct[i].mode = 0644; // Read by all, write by root
3050 + ct[i].ctl_name = CTL_SMC_PHY_STAT;
3051 + ct[i].procname = "phy_stat";
3052 + ct[i].data = (void*)&(lp->ctl_phy_stat);
3053 + ct[i].maxlen = sizeof lp->ctl_phy_stat;
3054 + ct[i].mode = 0644; // Read by all, write by root
3058 + ct[i].ctl_name = CTL_SMC_PHY_ID1;
3059 + ct[i].procname = "phy_id1";
3060 + ct[i].data = (void*)&(lp->ctl_phy_id1);
3061 + ct[i].maxlen = sizeof lp->ctl_phy_id1;
3062 + ct[i].mode = 0644; // Read by all, write by root
3066 + ct[i].ctl_name = CTL_SMC_PHY_ID2;
3067 + ct[i].procname = "phy_id2";
3068 + ct[i].data = (void*)&(lp->ctl_phy_id2);
3069 + ct[i].maxlen = sizeof lp->ctl_phy_id2;
3070 + ct[i].mode = 0644; // Read by all, write by root
3072 + // PHY Advertise Capabilities
3074 + ct[i].ctl_name = CTL_SMC_PHY_ADC;
3075 + ct[i].procname = "phy_adc";
3076 + ct[i].data = (void*)&(lp->ctl_phy_adc);
3077 + ct[i].maxlen = sizeof lp->ctl_phy_adc;
3078 + ct[i].mode = 0644; // Read by all, write by root
3080 + // PHY Remote Capabilities
3082 + ct[i].ctl_name = CTL_SMC_PHY_REMC;
3083 + ct[i].procname = "phy_remc";
3084 + ct[i].data = (void*)&(lp->ctl_phy_remc);
3085 + ct[i].maxlen = sizeof lp->ctl_phy_remc;
3086 + ct[i].mode = 0644; // Read by all, write by root
3088 + // PHY Configuration 1
3090 + ct[i].ctl_name = CTL_SMC_PHY_CFG1;
3091 + ct[i].procname = "phy_cfg1";
3092 + ct[i].data = (void*)&(lp->ctl_phy_cfg1);
3093 + ct[i].maxlen = sizeof lp->ctl_phy_cfg1;
3094 + ct[i].mode = 0644; // Read by all, write by root
3096 + // PHY Configuration 2
3098 + ct[i].ctl_name = CTL_SMC_PHY_CFG2;
3099 + ct[i].procname = "phy_cfg2";
3100 + ct[i].data = (void*)&(lp->ctl_phy_cfg2);
3101 + ct[i].maxlen = sizeof lp->ctl_phy_cfg2;
3102 + ct[i].mode = 0644; // Read by all, write by root
3104 + // PHY Interrupt/Status Output
3106 + ct[i].ctl_name = CTL_SMC_PHY_INT;
3107 + ct[i].procname = "phy_int";
3108 + ct[i].data = (void*)&(lp->ctl_phy_int);
3109 + ct[i].maxlen = sizeof lp->ctl_phy_int;
3110 + ct[i].mode = 0644; // Read by all, write by root
3112 + // PHY Interrupt/Status Mask
3114 + ct[i].ctl_name = CTL_SMC_PHY_MASK;
3115 + ct[i].procname = "phy_mask";
3116 + ct[i].data = (void*)&(lp->ctl_phy_mask);
3117 + ct[i].maxlen = sizeof lp->ctl_phy_mask;
3118 + ct[i].mode = 0644; // Read by all, write by root
3120 +#endif // SMC_DEBUG > 1
3122 + // Register /proc/sys/dev/ethX
3123 + lp->sysctl_header = register_sysctl_table(lp->root_table, 1);
3126 + // Register our modcount function which adjusts the module count
3127 + lp->root_table->child->de->fill_inode = smc_procfs_modcount;
3133 +/*------------------------------------------------------------
3134 + . Sysctl unregistration when driver is closed
3135 + .-------------------------------------------------------------*/
3136 +static void smc_sysctl_unregister(struct net_device *dev)
3138 + struct smc_local *lp = (struct smc_local *)dev->priv;
3140 + unregister_sysctl_table(lp->sysctl_header);
3143 +#endif /* endif CONFIG_SYSCTL */
3146 +//---PHY CONTROL AND CONFIGURATION-----------------------------------------
3148 +#if (SMC_DEBUG > 2 )
3150 +/*------------------------------------------------------------
3151 + . Debugging function for viewing MII Management serial bitstream
3152 + .-------------------------------------------------------------*/
3153 +static void smc_dump_mii_stream(byte* bits, int size)
3158 + for (i = 0; i < size; ++i)
3159 + printk("%d", i%10);
3161 + printk("\nMDOE:");
3162 + for (i = 0; i < size; ++i) {
3163 + if (bits[i] & MII_MDOE)
3169 + printk("\nMDO :");
3170 + for (i = 0; i < size; ++i) {
3171 + if (bits[i] & MII_MDO)
3177 + printk("\nMDI :");
3178 + for (i = 0; i < size; ++i) {
3179 + if (bits[i] & MII_MDI)
3189 +/*------------------------------------------------------------
3190 + . Reads a register from the MII Management serial interface
3191 + .-------------------------------------------------------------*/
3192 +static word smc_read_phy_register(unsigned long ioaddr,
3193 + byte phyaddr, byte phyreg)
3204 + // 32 consecutive ones on MDO to establish sync
3205 + for (i = 0; i < 32; ++i)
3206 + bits[clk_idx++] = MII_MDOE | MII_MDO;
3208 + // Start code <01>
3209 + bits[clk_idx++] = MII_MDOE;
3210 + bits[clk_idx++] = MII_MDOE | MII_MDO;
3212 + // Read command <10>
3213 + bits[clk_idx++] = MII_MDOE | MII_MDO;
3214 + bits[clk_idx++] = MII_MDOE;
3216 + // Output the PHY address, msb first
3217 + mask = (byte)0x10;
3218 + for (i = 0; i < 5; ++i) {
3219 + if (phyaddr & mask)
3220 + bits[clk_idx++] = MII_MDOE | MII_MDO;
3222 + bits[clk_idx++] = MII_MDOE;
3224 + // Shift to next lowest bit
3228 + // Output the phy register number, msb first
3229 + mask = (byte)0x10;
3230 + for (i = 0; i < 5; ++i) {
3231 + if (phyreg & mask)
3232 + bits[clk_idx++] = MII_MDOE | MII_MDO;
3234 + bits[clk_idx++] = MII_MDOE;
3236 + // Shift to next lowest bit
3240 + // Tristate and turnaround (2 bit times)
3241 + bits[clk_idx++] = 0;
3242 + //bits[clk_idx++] = 0;
3244 + // Input starts at this bit time
3245 + input_idx = clk_idx;
3247 + // Will input 16 bits
3248 + for (i = 0; i < 16; ++i)
3249 + bits[clk_idx++] = 0;
3251 + // Final clock bit
3252 + bits[clk_idx++] = 0;
3254 + // Save the current bank
3255 + oldBank = SMC_CURRENT_BANK();
3258 + SMC_SELECT_BANK( 3 );
3260 + // Get the current MII register value
3261 + mii_reg = SMC_GET_MII();
3263 + // Turn off all MII Interface bits
3264 + mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
3266 + // Clock all 64 cycles
3267 + for (i = 0; i < sizeof bits; ++i) {
3268 + // Clock Low - output data
3269 + SMC_SET_MII( mii_reg | bits[i] );
3273 + // Clock Hi - input data
3274 + SMC_SET_MII( mii_reg | bits[i] | MII_MCLK );
3276 + bits[i] |= SMC_GET_MII() & MII_MDI;
3279 + // Return to idle state
3280 + // Set clock to low, data to low, and output tristated
3281 + SMC_SET_MII( mii_reg );
3284 + // Restore original bank select
3285 + SMC_SELECT_BANK( oldBank );
3287 + // Recover input data
3289 + for (i = 0; i < 16; ++i) {
3292 + if (bits[input_idx++] & MII_MDI)
3293 + phydata |= 0x0001;
3296 +#if (SMC_DEBUG > 2 )
3297 + printk("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
3298 + phyaddr, phyreg, phydata);
3299 + smc_dump_mii_stream(bits, sizeof bits);
3306 +/*------------------------------------------------------------
3307 + . Writes a register to the MII Management serial interface
3308 + .-------------------------------------------------------------*/
3309 +static void smc_write_phy_register(unsigned long ioaddr,
3310 + byte phyaddr, byte phyreg, word phydata)
3319 + // 32 consecutive ones on MDO to establish sync
3320 + for (i = 0; i < 32; ++i)
3321 + bits[clk_idx++] = MII_MDOE | MII_MDO;
3323 + // Start code <01>
3324 + bits[clk_idx++] = MII_MDOE;
3325 + bits[clk_idx++] = MII_MDOE | MII_MDO;
3327 + // Write command <01>
3328 + bits[clk_idx++] = MII_MDOE;
3329 + bits[clk_idx++] = MII_MDOE | MII_MDO;
3331 + // Output the PHY address, msb first
3332 + mask = (byte)0x10;
3333 + for (i = 0; i < 5; ++i) {
3334 + if (phyaddr & mask)
3335 + bits[clk_idx++] = MII_MDOE | MII_MDO;
3337 + bits[clk_idx++] = MII_MDOE;
3339 + // Shift to next lowest bit
3343 + // Output the phy register number, msb first
3344 + mask = (byte)0x10;
3345 + for (i = 0; i < 5; ++i) {
3346 + if (phyreg & mask)
3347 + bits[clk_idx++] = MII_MDOE | MII_MDO;
3349 + bits[clk_idx++] = MII_MDOE;
3351 + // Shift to next lowest bit
3355 + // Tristate and turnaround (2 bit times)
3356 + bits[clk_idx++] = 0;
3357 + bits[clk_idx++] = 0;
3359 + // Write out 16 bits of data, msb first
3361 + for (i = 0; i < 16; ++i) {
3362 + if (phydata & mask)
3363 + bits[clk_idx++] = MII_MDOE | MII_MDO;
3365 + bits[clk_idx++] = MII_MDOE;
3367 + // Shift to next lowest bit
3371 + // Final clock bit (tristate)
3372 + bits[clk_idx++] = 0;
3374 + // Save the current bank
3375 + oldBank = SMC_CURRENT_BANK();
3378 + SMC_SELECT_BANK( 3 );
3380 + // Get the current MII register value
3381 + mii_reg = SMC_GET_MII();
3383 + // Turn off all MII Interface bits
3384 + mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
3386 + // Clock all cycles
3387 + for (i = 0; i < sizeof bits; ++i) {
3388 + // Clock Low - output data
3389 + SMC_SET_MII( mii_reg | bits[i] );
3393 + // Clock Hi - input data
3394 + SMC_SET_MII( mii_reg | bits[i] | MII_MCLK );
3396 + bits[i] |= SMC_GET_MII() & MII_MDI;
3399 + // Return to idle state
3400 + // Set clock to low, data to low, and output tristated
3401 + SMC_SET_MII( mii_reg );
3404 + // Restore original bank select
3405 + SMC_SELECT_BANK( oldBank );
3407 +#if (SMC_DEBUG > 2 )
3408 + printk("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
3409 + phyaddr, phyreg, phydata);
3410 + smc_dump_mii_stream(bits, sizeof bits);
3415 +/*------------------------------------------------------------
3416 + . Finds and reports the PHY address
3417 + .-------------------------------------------------------------*/
3418 +static int smc_detect_phy(struct net_device* dev)
3420 + struct smc_local *lp = (struct smc_local *)dev->priv;
3421 + unsigned long ioaddr = dev->base_addr;
3427 + PRINTK3("%s:smc_detect_phy()\n", dev->name);
3429 + // Scan all 32 PHY addresses if necessary
3430 + for (phyaddr = 0; phyaddr < 32; ++phyaddr) {
3431 + // Read the PHY identifiers
3432 + phy_id1 = smc_read_phy_register(ioaddr, phyaddr, PHY_ID1_REG);
3433 + phy_id2 = smc_read_phy_register(ioaddr, phyaddr, PHY_ID2_REG);
3435 + PRINTK3("%s: phy_id1=%x, phy_id2=%x\n",
3436 + dev->name, phy_id1, phy_id2);
3438 + // Make sure it is a valid identifier
3439 + if ((phy_id2 > 0x0000) && (phy_id2 < 0xffff) &&
3440 + (phy_id1 > 0x0000) && (phy_id1 < 0xffff)) {
3441 + if ((phy_id1 != 0x8000) && (phy_id2 != 0x8000)) {
3442 + // Save the PHY's address
3443 + lp->phyaddr = phyaddr;
3451 + PRINTK("%s: No PHY found\n", dev->name);
3455 + // Set the PHY type
3456 + if ( (phy_id1 == 0x0016) && ((phy_id2 & 0xFFF0) == 0xF840 ) ) {
3457 + lp->phytype = PHY_LAN83C183;
3458 + PRINTK("%s: PHY=LAN83C183 (LAN91C111 Internal)\n", dev->name);
3461 + if ( (phy_id1 == 0x0282) && ((phy_id2 & 0xFFF0) == 0x1C50) ) {
3462 + lp->phytype = PHY_LAN83C180;
3463 + PRINTK("%s: PHY=LAN83C180\n", dev->name);
3469 +/*------------------------------------------------------------
3470 + . Waits the specified number of milliseconds - kernel friendly
3471 + .-------------------------------------------------------------*/
3472 +static void smc_wait_ms(unsigned int ms)
3475 + if (!in_interrupt()) {
3476 + set_current_state(TASK_UNINTERRUPTIBLE);
3477 + schedule_timeout(1 + ms * HZ / 1000);
3479 + set_current_state(TASK_INTERRUPTIBLE);
3480 + schedule_timeout(1 + ms * HZ / 1000);
3481 + set_current_state(TASK_RUNNING);
3485 +/*------------------------------------------------------------
3486 + . Sets the PHY to a configuration as determined by the user
3487 + .-------------------------------------------------------------*/
3488 +static int smc_phy_fixed(struct net_device* dev)
3490 + unsigned long ioaddr = dev->base_addr;
3491 + struct smc_local *lp = (struct smc_local *)dev->priv;
3492 + byte phyaddr = lp->phyaddr;
3493 + word my_fixed_caps;
3496 + PRINTK3("%s:smc_phy_fixed()\n", dev->name);
3498 + // Enter Link Disable state
3499 + cfg1 = smc_read_phy_register(ioaddr, phyaddr, PHY_CFG1_REG);
3500 + cfg1 |= PHY_CFG1_LNKDIS;
3501 + smc_write_phy_register(ioaddr, phyaddr, PHY_CFG1_REG, cfg1);
3503 + // Set our fixed capabilities
3504 + // Disable auto-negotiation
3505 + my_fixed_caps = 0;
3507 + if (lp->ctl_rfduplx)
3508 + my_fixed_caps |= PHY_CNTL_DPLX;
3510 + if (lp->ctl_rspeed == 100)
3511 + my_fixed_caps |= PHY_CNTL_SPEED;
3513 + // Write our capabilities to the phy control register
3514 + smc_write_phy_register(ioaddr, phyaddr, PHY_CNTL_REG, my_fixed_caps);
3516 + // Re-Configure the Receive/Phy Control register
3517 + SMC_SET_RPC( lp->rpc_cur_mode );
3524 +/*------------------------------------------------------------
3525 + . Configures the specified PHY using Autonegotiation. Calls
3526 + . smc_phy_fixed() if the user has requested a certain config.
3527 + .-------------------------------------------------------------*/
3528 +static void smc_phy_configure(struct net_device* dev)
3530 + unsigned long ioaddr = dev->base_addr;
3531 + struct smc_local *lp = (struct smc_local *)dev->priv;
3534 + word my_phy_caps; // My PHY capabilities
3535 + word my_ad_caps; // My Advertised capabilities
3539 + PRINTK3("%s:smc_program_phy()\n", dev->name);
3541 + // Set the blocking flag
3542 + lp->autoneg_active = 1;
3544 + // Find the address and type of our phy
3545 + if (!smc_detect_phy(dev))
3546 + goto smc_phy_configure_exit;
3548 + // Get the detected phy address
3549 + phyaddr = lp->phyaddr;
3551 + // Reset the PHY, setting all other bits to zero
3552 + smc_write_phy_register(ioaddr, phyaddr, PHY_CNTL_REG, PHY_CNTL_RST);
3554 + // Wait for the reset to complete, or time out
3555 + timeout = 6; // Wait up to 3 seconds
3556 + while (timeout--) {
3557 + if (!(smc_read_phy_register(ioaddr, phyaddr, PHY_CNTL_REG)
3561 + smc_wait_ms(500); // wait 500 millisecs
3562 + if (signal_pending(current)) { // Exit anyway if signaled
3563 + PRINTK2("%s:PHY reset interrupted by signal\n",
3570 + if (timeout < 1) {
3571 + printk("%s:PHY reset timed out\n", dev->name);
3572 + goto smc_phy_configure_exit;
3575 + // Read PHY Register 18, Status Output
3576 + lp->lastPhy18 = smc_read_phy_register(ioaddr, phyaddr, PHY_INT_REG);
3578 + // Enable PHY Interrupts (for register 18)
3579 + // Interrupts listed here are disabled
3580 + smc_write_phy_register(ioaddr, phyaddr, PHY_MASK_REG,
3581 + PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD |
3582 + PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB |
3583 + PHY_INT_SPDDET | PHY_INT_DPLXDET);
3585 + /* Configure the Receive/Phy Control register */
3586 + SMC_SELECT_BANK( 0 );
3587 + SMC_SET_RPC( lp->rpc_cur_mode );
3589 + // Copy our capabilities from PHY_STAT_REG to PHY_AD_REG
3590 + my_phy_caps = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG);
3591 + my_ad_caps = PHY_AD_CSMA; // I am CSMA capable
3593 + if (my_phy_caps & PHY_STAT_CAP_T4)
3594 + my_ad_caps |= PHY_AD_T4;
3596 + if (my_phy_caps & PHY_STAT_CAP_TXF)
3597 + my_ad_caps |= PHY_AD_TX_FDX;
3599 + if (my_phy_caps & PHY_STAT_CAP_TXH)
3600 + my_ad_caps |= PHY_AD_TX_HDX;
3602 + if (my_phy_caps & PHY_STAT_CAP_TF)
3603 + my_ad_caps |= PHY_AD_10_FDX;
3605 + if (my_phy_caps & PHY_STAT_CAP_TH)
3606 + my_ad_caps |= PHY_AD_10_HDX;
3608 + // Disable capabilities not selected by our user
3609 + if (lp->ctl_rspeed != 100)
3610 + my_ad_caps &= ~(PHY_AD_T4|PHY_AD_TX_FDX|PHY_AD_TX_HDX);
3612 + if (!lp->ctl_rfduplx)
3613 + my_ad_caps &= ~(PHY_AD_TX_FDX|PHY_AD_10_FDX);
3615 + // Update our Auto-Neg Advertisement Register
3616 + smc_write_phy_register(ioaddr, phyaddr, PHY_AD_REG, my_ad_caps);
3618 + // Read the register back. Without this, it appears that when
3619 + // auto-negotiation is restarted, sometimes it isn't ready and
3620 + // the link does not come up.
3621 + status = smc_read_phy_register(ioaddr, phyaddr, PHY_AD_REG);
3623 + PRINTK2("%s:phy caps=%x\n", dev->name, my_phy_caps);
3624 + PRINTK2("%s:phy advertised caps=%x\n", dev->name, my_ad_caps);
3626 + // If the user requested no auto neg, then go set his request
3627 + if (!(lp->ctl_autoneg)) {
3628 + smc_phy_fixed(dev);
3629 + goto smc_phy_configure_exit;
3632 + // Restart auto-negotiation process in order to advertise my caps
3633 + smc_write_phy_register( ioaddr, phyaddr, PHY_CNTL_REG,
3634 + PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST );
3636 + // Wait for the auto-negotiation to complete. This may take from
3637 + // 2 to 3 seconds.
3638 + // Wait for the reset to complete, or time out
3639 + timeout = 20; // Wait up to 10 seconds
3640 + while (timeout--) {
3641 + status = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG);
3642 + if (status & PHY_STAT_ANEG_ACK)
3643 + // auto-negotiate complete
3646 + smc_wait_ms(500); // wait 500 millisecs
3647 + if (signal_pending(current)) { // Exit anyway if signaled
3649 + "%s:PHY auto-negotiate interrupted by signal\n",
3655 + // Restart auto-negotiation if remote fault
3656 + if (status & PHY_STAT_REM_FLT) {
3657 + PRINTK2("%s:PHY remote fault detected\n", dev->name);
3659 + // Restart auto-negotiation
3660 + PRINTK2("%s:PHY restarting auto-negotiation\n",
3662 + smc_write_phy_register( ioaddr, phyaddr, PHY_CNTL_REG,
3663 + PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST |
3664 + PHY_CNTL_SPEED | PHY_CNTL_DPLX);
3668 + if (timeout < 1) {
3669 + printk(KERN_DEBUG "%s:PHY auto-negotiate timed out\n",
3671 + PRINTK2("%s:PHY auto-negotiate timed out\n", dev->name);
3675 + // Fail if we detected an auto-negotiate remote fault
3676 + if (status & PHY_STAT_REM_FLT) {
3677 + printk(KERN_DEBUG "%s:PHY remote fault detected\n", dev->name);
3678 + PRINTK2("%s:PHY remote fault detected\n", dev->name);
3682 + // The smc_phy_interrupt() routine will be called to update lastPhy18
3684 + // Set our sysctl parameters to match auto-negotiation results
3685 + if ( lp->lastPhy18 & PHY_INT_SPDDET ) {
3686 + PRINTK2("%s:PHY 100BaseT\n", dev->name);
3687 + lp->rpc_cur_mode |= RPC_SPEED;
3689 + PRINTK2("%s:PHY 10BaseT\n", dev->name);
3690 + lp->rpc_cur_mode &= ~RPC_SPEED;
3693 + if ( lp->lastPhy18 & PHY_INT_DPLXDET ) {
3694 + PRINTK2("%s:PHY Full Duplex\n", dev->name);
3695 + lp->rpc_cur_mode |= RPC_DPLX;
3697 + PRINTK2("%s:PHY Half Duplex\n", dev->name);
3698 + lp->rpc_cur_mode &= ~RPC_DPLX;
3701 + // Re-Configure the Receive/Phy Control register
3702 + SMC_SET_RPC( lp->rpc_cur_mode );
3704 +smc_phy_configure_exit:
3705 + // Exit auto-negotiation
3706 + lp->autoneg_active = 0;
3711 +/*************************************************************************
3712 + . smc_phy_interrupt
3714 + . Purpose: Handle interrupts relating to PHY register 18. This is
3715 + . called from the "hard" interrupt handler.
3717 + ************************************************************************/
3718 +static void smc_phy_interrupt(struct net_device* dev)
3720 + unsigned long ioaddr = dev->base_addr;
3721 + struct smc_local *lp = (struct smc_local *)dev->priv;
3722 + byte phyaddr = lp->phyaddr;
3725 + PRINTK2("%s: smc_phy_interrupt\n", dev->name);
3728 + // Read PHY Register 18, Status Output
3729 + phy18 = smc_read_phy_register(ioaddr, phyaddr, PHY_INT_REG);
3731 + // Exit if not more changes
3732 + if (phy18 == lp->lastPhy18)
3735 +#if (SMC_DEBUG > 1 )
3736 + PRINTK2("%s: phy18=0x%x\n", dev->name, phy18);
3737 + PRINTK2("%s: lastPhy18=0x%x\n", dev->name, lp->lastPhy18);
3740 + if ((phy18 & PHY_INT_LNKFAIL) !=
3741 + (lp->lastPhy18 & PHY_INT_LNKFAIL))
3742 + PRINTK2("%s: PHY Link Fail=%x\n", dev->name,
3743 + phy18 & PHY_INT_LNKFAIL);
3745 + if ((phy18 & PHY_INT_LOSSSYNC) !=
3746 + (lp->lastPhy18 & PHY_INT_LOSSSYNC))
3747 + PRINTK2("%s: PHY LOSS SYNC=%x\n", dev->name,
3748 + phy18 & PHY_INT_LOSSSYNC);
3750 + if ((phy18 & PHY_INT_CWRD) != (lp->lastPhy18 & PHY_INT_CWRD))
3751 + PRINTK2("%s: PHY INVALID 4B5B code=%x\n", dev->name,
3752 + phy18 & PHY_INT_CWRD);
3754 + if ((phy18 & PHY_INT_SSD) != (lp->lastPhy18 & PHY_INT_SSD))
3755 + PRINTK2("%s: PHY No Start Of Stream=%x\n", dev->name,
3756 + phy18 & PHY_INT_SSD);
3758 + if ((phy18 & PHY_INT_ESD) != (lp->lastPhy18 & PHY_INT_ESD))
3760 + PRINTK2("%s: PHY No End Of Stream=%x\n", dev->name,
3761 + phy18 & PHY_INT_ESD);
3763 + if ((phy18 & PHY_INT_RPOL) != (lp->lastPhy18 & PHY_INT_RPOL))
3764 + PRINTK2("%s: PHY Reverse Polarity Detected=%x\n",
3765 + dev->name, phy18 & PHY_INT_RPOL);
3767 + if ((phy18 & PHY_INT_JAB) != (lp->lastPhy18 & PHY_INT_JAB))
3768 + PRINTK2("%s: PHY Jabber Detected=%x\n", dev->name,
3769 + phy18 & PHY_INT_JAB);
3771 + if ((phy18 & PHY_INT_SPDDET) !=
3772 + (lp->lastPhy18 & PHY_INT_SPDDET))
3773 + PRINTK2("%s: PHY Speed Detect=%x\n", dev->name,
3774 + phy18 & PHY_INT_SPDDET);
3776 + if ((phy18 & PHY_INT_DPLXDET) !=
3777 + (lp->lastPhy18 & PHY_INT_DPLXDET))
3778 + PRINTK2("%s: PHY Duplex Detect=%x\n", dev->name,
3779 + phy18 & PHY_INT_DPLXDET);
3781 + // Update the last phy 18 variable
3782 + lp->lastPhy18 = phy18;
3785 diff -Narup linux-2.4.31-orig/drivers/net/smc91111.h linux-2.4.31/drivers/net/smc91111.h
3786 --- linux-2.4.31-orig/drivers/net/smc91111.h 1969-12-31 16:00:00.000000000 -0800
3787 +++ linux-2.4.31/drivers/net/smc91111.h 2005-08-08 16:03:33.000000000 -0700
3789 +/*------------------------------------------------------------------------
3790 + . smc91111.h - macros for the LAN91C111 Ethernet Driver
3792 + . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
3793 + . Developed by Simple Network Magic Corporation (SNMC)
3794 + . Copyright (C) 1996 by Erik Stahlman (ES)
3796 + . This program is free software; you can redistribute it and/or modify
3797 + . it under the terms of the GNU General Public License as published by
3798 + . the Free Software Foundation; either version 2 of the License, or
3799 + . (at your option) any later version.
3801 + . This program is distributed in the hope that it will be useful,
3802 + . but WITHOUT ANY WARRANTY; without even the implied warranty of
3803 + . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3804 + . GNU General Public License for more details.
3806 + . You should have received a copy of the GNU General Public License
3807 + . along with this program; if not, write to the Free Software
3808 + . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3810 + . This file contains register information and access macros for
3811 + . the LAN91C111 single chip ethernet controller. It is a modified
3812 + . version of the smc9194.h file.
3814 + . Information contained in this file was obtained from the LAN91C111
3815 + . manual from SMC. To get a copy, if you really want one, you can find
3816 + . information under www.smsc.com.
3819 + . Erik Stahlman ( erik@vt.edu )
3820 + . Daris A Nevil ( dnevil@snmc.com )
3823 + . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device
3825 + ---------------------------------------------------------------------------*/
3826 +#ifndef _SMC91111_H_
3827 +#define _SMC91111_H_
3829 +/* I want some simple types */
3831 +typedef unsigned char byte;
3832 +typedef unsigned short word;
3833 +typedef unsigned long int dword;
3837 + . Do you want to use 8 bit xfers? This should work on all chips, as the
3838 + . chipset is designed to accommodate them, although some hardware engineers
3839 + . do not connect byte enables so 8 bit xfers can not be used.
3841 +#ifdef CONFIG_SMC91111_USE_8_BIT
3842 +#define SMC_inb(port) inb(port)
3843 +#define SMC_insb(port,buf,ns) insb((port),(buf),(ns))
3844 +#define SMC_outb(val,port) outb((val),(port))
3845 +#define SMC_outsb(port,buf,ns) outsb((port),(buf),(ns))
3846 +#endif /* CONFIG_SMC91111_USE_8_BIT */
3848 +/* Define 16 bit xfers. */
3849 +#ifdef CONFIG_SMC91111_BYTE_SWAP
3850 +#define SMC_inw(port) swab16(inw(port))
3851 +#define SMC_insw(port,buf,ns) \
3853 + unsigned long __port = (port); \
3854 + word *__buf = (word *)(buf); \
3855 + int __ns = (ns); \
3856 + insw(__port,__buf,__ns); \
3857 + while (__ns > 0) { \
3858 + *__buf = swab16(*__buf); \
3863 +#define SMC_outw(val,port) outw(swab16(val),(port))
3864 +#define SMC_outsw(port,buf,ns) \
3866 + unsigned long __port = (port); \
3867 + word *__buf = (word *)(buf); \
3868 + int __ns = (ns); \
3869 + while (__ns > 0) { \
3870 + /* Believe it or not, the swab isn't needed. */ \
3871 + outw( /* swab16 */ (*__buf++), __port); \
3875 +#else /* CONFIG_SMC91111_BYTE_SWAP is not defined */
3876 +#define SMC_inw(port) inw(port)
3877 +#define SMC_insw(port,buf,ns) insw((port),(buf),(ns))
3878 +#define SMC_outw(val,port) outw((val),(port))
3879 +#define SMC_outsw(port,buf,ns) outsw((port),(buf),(ns))
3880 +#endif /* CONFIG_SMC91111_BYTE_SWAP */
3883 + . Do you want to use 32 bit xfers? This should work on all chips, as the
3884 + . chipset is designed to accommodate them, although some hardware engineers
3885 + . do not connect all 32 data bits so 32 bit xfers can not be used.
3887 +#ifdef CONFIG_SMC91111_USE_32_BIT
3888 +#ifdef CONFIG_SMC91111_BYTE_SWAP
3889 +#define SMC_inl(port) swab32(inl(port))
3890 +#define SMC_insl(port,buf,ns) \
3892 + unsigned long __port = (port); \
3893 + dword *__buf = (dword *)(buf); \
3894 + int __ns = (ns); \
3895 + insl(__port,__buf,__ns); \
3896 + while (__ns > 0) { \
3897 + *__buf = swab32(*__buf); \
3902 +#define SMC_outl(val,port) outl(swab32(val),(port))
3903 +#define SMC_outsl(port,buf,ns) \
3905 + unsigned long __port = (port); \
3906 + dword *__buf = (dword *)(buf); \
3907 + int __ns = (ns); \
3908 + while (__ns > 0) { \
3909 + /* Believe it or not, the swab isn't needed. */ \
3910 + outl( /* swab32 */ (*__buf++), __port); \
3914 +#else /* CONFIG_SMC91111_BYTE_SWAP is not defined */
3915 +#define SMC_inl(port) inl(port)
3916 +#define SMC_insl(port,buf,ns) insl((port),(buf),(ns))
3917 +#define SMC_outl(val,port) outl((val),(port))
3918 +#define SMC_outsl(port,buf,ns) outsl((port),(buf),(ns))
3919 +#endif /* CONFIG_SMC91111_BYTE_SWAP */
3920 +#endif /* CONFIG_SMC91111_USE_32_BIT */
3923 +/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
3925 +#define SMC_IO_EXTENT 16
3928 +/*---------------------------------------------------------------
3930 + . A description of the SMSC registers is probably in order here,
3931 + . although for details, the SMC datasheet is invaluable.
3933 + . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
3934 + . are accessed by writing a number into the BANK_SELECT register
3935 + . ( I also use a SMC_SELECT_BANK macro for this ).
3937 + . The banks are configured so that for most purposes, bank 2 is all
3938 + . that is needed for simple run time tasks.
3939 + -----------------------------------------------------------------------*/
3942 + . Bank Select Register:
3944 + . yyyy yyyy 0000 00xx
3945 + . xx = bank number
3946 + . yyyy yyyy = 0x33, for identification purposes.
3948 +#define BANK_SELECT 14
3950 +// Transmit Control Register
3952 +#define TCR_REG 0x0000 // transmit control register
3953 +#define TCR_ENABLE 0x0001 // When 1 we can transmit
3954 +#define TCR_LOOP 0x0002 // Controls output pin LBK
3955 +#define TCR_FORCOL 0x0004 // When 1 will force a collision
3956 +#define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
3957 +#define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
3958 +#define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
3959 +#define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
3960 +#define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
3961 +#define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
3962 +#define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
3964 +#define TCR_CLEAR 0 /* do NOTHING */
3965 +/* the default settings for the TCR register : */
3966 +/* QUESTION: do I want to enable padding of short packets ? */
3967 +#define TCR_DEFAULT TCR_ENABLE
3970 +// EPH Status Register
3972 +#define EPH_STATUS_REG 0x0002
3973 +#define ES_TX_SUC 0x0001 // Last TX was successful
3974 +#define ES_SNGL_COL 0x0002 // Single collision detected for last tx
3975 +#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
3976 +#define ES_LTX_MULT 0x0008 // Last tx was a multicast
3977 +#define ES_16COL 0x0010 // 16 Collisions Reached
3978 +#define ES_SQET 0x0020 // Signal Quality Error Test
3979 +#define ES_LTXBRD 0x0040 // Last tx was a broadcast
3980 +#define ES_TXDEFR 0x0080 // Transmit Deferred
3981 +#define ES_LATCOL 0x0200 // Late collision detected on last tx
3982 +#define ES_LOSTCARR 0x0400 // Lost Carrier Sense
3983 +#define ES_EXC_DEF 0x0800 // Excessive Deferral
3984 +#define ES_CTR_ROL 0x1000 // Counter Roll Over indication
3985 +#define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
3986 +#define ES_TXUNRN 0x8000 // Tx Underrun
3989 +// Receive Control Register
3991 +#define RCR_REG 0x0004
3992 +#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
3993 +#define RCR_PRMS 0x0002 // Enable promiscuous mode
3994 +#define RCR_ALMUL 0x0004 // When set accepts all multicast frames
3995 +#define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
3996 +#define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
3997 +#define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
3998 +#define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
3999 +#define RCR_SOFTRST 0x8000 // resets the chip
4001 +/* the normal settings for the RCR register : */
4002 +#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
4003 +#define RCR_CLEAR 0x0 // set it to a base state
4005 +// Counter Register
4007 +#define COUNTER_REG 0x0006
4009 +// Memory Information Register
4011 +#define MIR_REG 0x0008
4013 +// Receive/Phy Control Register
4015 +#define RPC_REG 0x000A
4016 +#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
4017 +#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
4018 +#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
4019 +#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
4020 +#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
4021 +#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
4022 +#define RPC_LED_RES (0x01) // LED = Reserved
4023 +#define RPC_LED_10 (0x02) // LED = 10Mbps link detect
4024 +#define RPC_LED_FD (0x03) // LED = Full Duplex Mode
4025 +#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
4026 +#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
4027 +#define RPC_LED_TX (0x06) // LED = TX packet occurred
4028 +#define RPC_LED_RX (0x07) // LED = RX packet occurred
4029 +#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
4031 +/* Bank 0 0x000C is reserved */
4033 +// Bank Select Register
4035 +#define BSR_REG 0x000E
4038 +// Configuration Reg
4040 +#define CONFIG_REG 0x0000
4041 +#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
4042 +#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
4043 +#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
4044 +#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
4046 +// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
4047 +#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
4050 +// Base Address Register
4052 +#define BASE_REG 0x0002
4055 +// Individual Address Registers
4057 +#define ADDR0_REG 0x0004
4058 +#define ADDR1_REG 0x0006
4059 +#define ADDR2_REG 0x0008
4062 +// General Purpose Register
4064 +#define GP_REG 0x000A
4067 +// Control Register
4069 +#define CTL_REG 0x000C
4070 +#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
4071 +#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
4072 +#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
4073 +#define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
4074 +#define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
4075 +#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
4076 +#define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
4077 +#define CTL_STORE 0x0001 // When set stores registers into EEPROM
4080 +// MMU Command Register
4082 +#define MMU_CMD_REG 0x0000
4083 +#define MC_BUSY 1 // When 1 the last release has not completed
4084 +#define MC_NOP (0<<5) // No Op
4085 +#define MC_ALLOC (1<<5) // OR with number of 256 byte packets
4086 +#define MC_RESET (2<<5) // Reset MMU to initial state
4087 +#define MC_REMOVE (3<<5) // Remove the current rx packet
4088 +#define MC_RELEASE (4<<5) // Remove and release the current rx packet
4089 +#define MC_FREEPKT (5<<5) // Release packet in PNR register
4090 +#define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
4091 +#define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
4094 +// Packet Number Register
4096 +#define PN_REG 0x0002
4099 +// Allocation Result Register
4101 +#define AR_REG 0x0003
4102 +#define AR_FAILED 0x80 // Alocation Failed
4105 +// RX FIFO Ports Register
4107 +#define RXFIFO_REG 0x0004 // Must be read as a word
4108 +#define RXFIFO_REMPTY 0x8000 // RX FIFO Empty
4111 +// TX FIFO Ports Register
4113 +#define TXFIFO_REG RXFIFO_REG // Must be read as a word
4114 +#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
4117 +// Pointer Register
4119 +#define PTR_REG 0x0006
4120 +#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
4121 +#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
4122 +#define PTR_READ 0x2000 // When 1 the operation is a read
4127 +#define DATA_REG 0x0008
4130 +// Interrupt Status/Acknowledge Register
4132 +#define INT_REG 0x000C
4135 +// Interrupt Mask Register
4137 +#define IM_REG 0x000D
4138 +#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
4139 +#define IM_ERCV_INT 0x40 // Early Receive Interrupt
4140 +#define IM_EPH_INT 0x20 // Set by Etheret Protocol Handler section
4141 +#define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
4142 +#define IM_ALLOC_INT 0x08 // Set when allocation request is completed
4143 +#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
4144 +#define IM_TX_INT 0x02 // Transmit Interrrupt
4145 +#define IM_RCV_INT 0x01 // Receive Interrupt
4148 +// Multicast Table Registers
4150 +#define MCAST_REG1 0x0000
4151 +#define MCAST_REG2 0x0002
4152 +#define MCAST_REG3 0x0004
4153 +#define MCAST_REG4 0x0006
4156 +// Management Interface Register (MII)
4158 +#define MII_REG 0x0008
4159 +#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
4160 +#define MII_MDOE 0x0008 // MII Output Enable
4161 +#define MII_MCLK 0x0004 // MII Clock, pin MDCLK
4162 +#define MII_MDI 0x0002 // MII Input, pin MDI
4163 +#define MII_MDO 0x0001 // MII Output, pin MDO
4166 +// Revision Register
4168 +#define REV_REG 0x000A /* ( hi: chip id low: rev # ) */
4171 +// Early RCV Register
4173 +/* this is NOT on SMC9192 */
4174 +#define ERCV_REG 0x000C
4175 +#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
4176 +#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
4178 +// External Register
4180 +#define EXT_REG 0x0000
4183 +#define CHIP_9192 3
4184 +#define CHIP_9194 4
4185 +#define CHIP_9195 5
4186 +#define CHIP_9196 6
4187 +#define CHIP_91100 7
4188 +#define CHIP_91100FD 8
4189 +#define CHIP_91111FD 9
4191 +static const char * chip_ids[ 15 ] = {
4193 + /* 3 */ "SMC91C90/91C92",
4194 + /* 4 */ "SMC91C94",
4195 + /* 5 */ "SMC91C95",
4196 + /* 6 */ "SMC91C96",
4197 + /* 7 */ "SMC91C100",
4198 + /* 8 */ "SMC91C100FD",
4199 + /* 9 */ "SMC91C11xFD",
4201 + NULL, NULL, NULL};
4204 + . Transmit status bits
4206 +#define TS_SUCCESS 0x0001
4207 +#define TS_LOSTCAR 0x0400
4208 +#define TS_LATCOL 0x0200
4209 +#define TS_16COL 0x0010
4212 + . Receive status bits
4214 +#define RS_ALGNERR 0x8000
4215 +#define RS_BRODCAST 0x4000
4216 +#define RS_BADCRC 0x2000
4217 +#define RS_ODDFRAME 0x1000 // bug: the LAN91C111 never sets this on receive
4218 +#define RS_TOOLONG 0x0800
4219 +#define RS_TOOSHORT 0x0400
4220 +#define RS_MULTICAST 0x0001
4221 +#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
4226 + PHY_LAN83C183 = 1, // LAN91C111 Internal PHY
4231 +// PHY Register Addresses (LAN91C111 Internal PHY)
4233 +// PHY Control Register
4234 +#define PHY_CNTL_REG 0x00
4235 +#define PHY_CNTL_RST 0x8000 // 1=PHY Reset
4236 +#define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback
4237 +#define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs
4238 +#define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation
4239 +#define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode
4240 +#define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled
4241 +#define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate
4242 +#define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex
4243 +#define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test
4245 +// PHY Status Register
4246 +#define PHY_STAT_REG 0x01
4247 +#define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable
4248 +#define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable
4249 +#define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable
4250 +#define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable
4251 +#define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable
4252 +#define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble
4253 +#define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed
4254 +#define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected
4255 +#define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable
4256 +#define PHY_STAT_LINK 0x0004 // 1=valid link
4257 +#define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition
4258 +#define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented
4260 +// PHY Identifier Registers
4261 +#define PHY_ID1_REG 0x02 // PHY Identifier 1
4262 +#define PHY_ID2_REG 0x03 // PHY Identifier 2
4264 +// PHY Auto-Negotiation Advertisement Register
4265 +#define PHY_AD_REG 0x04
4266 +#define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page
4267 +#define PHY_AD_ACK 0x4000 // 1=got link code word from remote
4268 +#define PHY_AD_RF 0x2000 // 1=advertise remote fault
4269 +#define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4
4270 +#define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX
4271 +#define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX
4272 +#define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX
4273 +#define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX
4274 +#define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA
4276 +// PHY Auto-negotiation Remote End Capability Register
4277 +#define PHY_RMT_REG 0x05
4278 +// Uses same bit definitions as PHY_AD_REG
4280 +// PHY Configuration Register 1
4281 +#define PHY_CFG1_REG 0x10
4282 +#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
4283 +#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
4284 +#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
4285 +#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
4286 +#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
4287 +#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
4288 +#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
4289 +#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
4290 +#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
4291 +#define PHY_CFG1_TLVL_MASK 0x003C
4292 +#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
4295 +// PHY Configuration Register 2
4296 +#define PHY_CFG2_REG 0x11
4297 +#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
4298 +#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
4299 +#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
4300 +#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
4302 +// PHY Status Output (and Interrupt status) Register
4303 +#define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
4304 +#define PHY_INT_INT 0x8000 // 1=bits have changed since last read
4305 +#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
4306 +#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
4307 +#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
4308 +#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
4309 +#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
4310 +#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
4311 +#define PHY_INT_JAB 0x0100 // 1=Jabber detected
4312 +#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
4313 +#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
4315 +// PHY Interrupt/Status Mask Register
4316 +#define PHY_MASK_REG 0x13 // Interrupt Mask
4317 +// Uses the same bit definitions as PHY_INT_REG
4321 +/*-------------------------------------------------------------------------
4322 + . I define some macros to make it easier to do somewhat common
4323 + . or slightly complicated, repeated tasks.
4324 + --------------------------------------------------------------------------*/
4326 +/* select a register bank, 0 to 3 */
4328 +#define SMC_SELECT_BANK(x) { SMC_outw( x, ioaddr + BANK_SELECT ); }
4329 +#define SMC_CURRENT_BANK() SMC_inw( ioaddr + BANK_SELECT )
4331 +/* this enables an interrupt in the interrupt mask register */
4332 +#define SMC_ENABLE_INT(x) {\
4333 + unsigned char mask;\
4334 + SMC_SELECT_BANK(2);\
4335 + mask = SMC_GET_INT_MASK();\
4337 + SMC_SET_INT_MASK(mask); \
4340 +/* this disables an interrupt from the interrupt mask register */
4342 +#define SMC_DISABLE_INT(x) {\
4343 + unsigned char mask;\
4344 + SMC_SELECT_BANK(2);\
4345 + mask = SMC_GET_INT_MASK();\
4347 + SMC_SET_INT_MASK(mask); \
4350 +/* Note: the following macros do *not* select the bank. */
4352 +#define SMC_GET_PN() SMC_inb( ioaddr + PN_REG )
4353 +#define SMC_SET_PN(x) SMC_outb( (x), ioaddr + PN_REG )
4354 +#define SMC_GET_AR() SMC_inb( ioaddr + AR_REG )
4355 +#define SMC_GET_INT() SMC_inb( ioaddr + INT_REG )
4356 +#define SMC_ACK_INT(x) SMC_outb( (x), ioaddr + INT_REG )
4357 +#define SMC_GET_INT_MASK() SMC_inb( ioaddr + IM_REG )
4358 +#define SMC_SET_INT_MASK(x) SMC_outb( (x), ioaddr + IM_REG )
4360 +#define SMC_GET_PN() (SMC_inw( ioaddr + PN_REG ) & 0xFF)
4361 +#define SMC_SET_PN(x) SMC_outw( (x), ioaddr + PN_REG )
4362 +#define SMC_GET_AR() (SMC_inw( ioaddr + PN_REG ) >> 8)
4363 +#define SMC_GET_INT() (SMC_inw( ioaddr + INT_REG ) & 0xFF)
4364 +#define SMC_ACK_INT(x) SMC_outw( (SMC_GET_INT_MASK() << 8) | (x), \
4365 + ioaddr + INT_REG )
4366 +#define SMC_GET_INT_MASK() (SMC_inw( ioaddr + INT_REG ) >> 8)
4367 +#define SMC_SET_INT_MASK(x) SMC_outw( (x) << 8, ioaddr + INT_REG )
4370 +#define SMC_GET_BASE() SMC_inw( ioaddr + BASE_REG)
4371 +#define SMC_SET_BASE(x) SMC_outw( (x), ioaddr + BASE_REG)
4372 +#define SMC_GET_CONFIG() SMC_inw( ioaddr + CONFIG_REG)
4373 +#define SMC_SET_CONFIG(x) SMC_outw( (x), ioaddr + CONFIG_REG)
4374 +#define SMC_GET_COUNTER() SMC_inw( ioaddr + COUNTER_REG)
4375 +#define SMC_SET_COUNTER(x) SMC_outw( (x), ioaddr + COUNTER_REG)
4376 +#define SMC_GET_CTL() SMC_inw( ioaddr + CTL_REG)
4377 +#define SMC_SET_CTL(x) SMC_outw( (x), ioaddr + CTL_REG)
4378 +#define SMC_GET_MII() SMC_inw( ioaddr + MII_REG)
4379 +#define SMC_SET_MII(x) SMC_outw( (x), ioaddr + MII_REG)
4380 +#define SMC_GET_MIR() SMC_inw( ioaddr + MIR_REG)
4381 +#define SMC_SET_MIR(x) SMC_outw( (x), ioaddr + MIR_REG)
4382 +#define SMC_GET_MMU_CMD() SMC_inw( ioaddr + MMU_CMD_REG)
4383 +#define SMC_SET_MMU_CMD(x) SMC_outw( (x), ioaddr + MMU_CMD_REG)
4384 +#define SMC_GET_PTR() SMC_inw( ioaddr + PTR_REG)
4385 +#define SMC_SET_PTR(x) SMC_outw( (x), ioaddr + PTR_REG)
4386 +#define SMC_GET_RCR() SMC_inw( ioaddr + RCR_REG)
4387 +#define SMC_SET_RCR(x) SMC_outw( (x), ioaddr + RCR_REG)
4388 +#define SMC_GET_REV() SMC_inw( ioaddr + REV_REG)
4389 +#define SMC_SET_REV(x) SMC_outw( (x), ioaddr + REV_REG)
4390 +#define SMC_GET_RPC() SMC_inw( ioaddr + RPC_REG)
4391 +#define SMC_SET_RPC(x) SMC_outw( (x), ioaddr + RPC_REG)
4392 +#define SMC_GET_RXFIFO() SMC_inw( ioaddr + RXFIFO_REG)
4393 +#define SMC_SET_RXFIFO(x) SMC_outw( (x), ioaddr + RXFIFO_REG)
4394 +#define SMC_GET_TCR() SMC_inw( ioaddr + TCR_REG)
4395 +#define SMC_SET_TCR(x) SMC_outw( (x), ioaddr + TCR_REG)
4397 +#define SMC_CLEAR_MCAST() {\
4398 + SMC_outw( 0, ioaddr + MCAST_REG1); \
4399 + SMC_outw( 0, ioaddr + MCAST_REG2); \
4400 + SMC_outw( 0, ioaddr + MCAST_REG3); \
4401 + SMC_outw( 0, ioaddr + MCAST_REG4); \
4403 +#define SMC_SET_MCAST(x) {\
4406 + unsigned char *mt = (x);\
4407 + for ( i = 0; i < 8; i += 2 ) {\
4408 + w = mt[i] | (mt[i + 1] << 8);\
4409 + SMC_outw( w, ioaddr + MCAST_REG1 + i );\
4414 +/*----------------------------------------------------------------------
4415 + . Define the interrupts that I want to receive from the card
4418 + . IM_EPH_INT, for nasty errors
4419 + . IM_RCV_INT, for happy received packets
4420 + . IM_RX_OVRN_INT, because I have to kick the receiver
4421 + . IM_MDINT, for PHY Register 18 Status Changes
4422 + --------------------------------------------------------------------------*/
4423 +#define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
4427 +#ifdef CONFIG_SYSCTL
4429 + * Declarations for the sysctl interface, which allows users the ability to
4430 + * control the finer aspects of the LAN91C111 chip. Since the smc
4431 + * module currently registers its sysctl table dynamically, the sysctl path
4432 + * for module FOO is /proc/sys/dev/ethX/FOO
4434 +#define CTL_SMC (CTL_BUS+1389) // arbitrary and hopefully unused
4437 + CTL_SMC_INFO = 1, // Sysctl files information
4438 + CTL_SMC_SWVER, // Driver Software Version Info
4439 + CTL_SMC_SWFDUP, // Switched Full Duplex Mode
4440 + CTL_SMC_EPHLOOP, // EPH Block Internal Loopback
4441 + CTL_SMC_MIIOP, // MII Operation
4442 + CTL_SMC_AUTONEG, // Auto-negotiate Mode
4443 + CTL_SMC_RFDUPLX, // Request Full Duplex Mode
4444 + CTL_SMC_RSPEED, // Request Speed Selection
4445 + CTL_SMC_AFDUPLX, // Actual Full Duplex Mode
4446 + CTL_SMC_ASPEED, // Actual Speed Selection
4447 + CTL_SMC_LNKFAIL, // Link Failed
4448 + CTL_SMC_FORCOL, // Force a Collision
4449 + CTL_SMC_FILTCAR, // Filter Carrier
4450 + CTL_SMC_FREEMEM, // Free Buffer Memory
4451 + CTL_SMC_TOTMEM, // Total Buffer Memory
4452 + CTL_SMC_LEDA, // Output of LED-A
4453 + CTL_SMC_LEDB, // Output of LED-B
4454 + CTL_SMC_CHIPREV, // LAN91C111 Chip Revision ID
4456 + // Register access for debugging
4457 + CTL_SMC_REG_BSR, // Bank Select
4458 + CTL_SMC_REG_TCR, // Transmit Control
4459 + CTL_SMC_REG_ESR, // EPH Status
4460 + CTL_SMC_REG_RCR, // Receive Control
4461 + CTL_SMC_REG_CTRR, // Counter
4462 + CTL_SMC_REG_MIR, // Memory Information
4463 + CTL_SMC_REG_RPCR, // Receive/Phy Control
4464 + CTL_SMC_REG_CFGR, // Configuration
4465 + CTL_SMC_REG_BAR, // Base Address
4466 + CTL_SMC_REG_IAR0, // Individual Address 0
4467 + CTL_SMC_REG_IAR1, // Individual Address 1
4468 + CTL_SMC_REG_IAR2, // Individual Address 2
4469 + CTL_SMC_REG_GPR, // General Purpose
4470 + CTL_SMC_REG_CTLR, // Control
4471 + CTL_SMC_REG_MCR, // MMU Command
4472 + CTL_SMC_REG_PNR, // Packet Number
4473 + CTL_SMC_REG_FPR, // FIFO Ports
4474 + CTL_SMC_REG_PTR, // Pointer
4475 + CTL_SMC_REG_DR, // Data
4476 + CTL_SMC_REG_ISR, // Interrupt Status
4477 + CTL_SMC_REG_MTR1, // Multicast Table Entry 1
4478 + CTL_SMC_REG_MTR2, // Multicast Table Entry 2
4479 + CTL_SMC_REG_MTR3, // Multicast Table Entry 3
4480 + CTL_SMC_REG_MTR4, // Multicast Table Entry 4
4481 + CTL_SMC_REG_MIIR, // Management Interface
4482 + CTL_SMC_REG_REVR, // Revision
4483 + CTL_SMC_REG_ERCVR, // Early RCV
4484 + CTL_SMC_REG_EXTR, // External
4485 + CTL_SMC_PHY_CTRL, // PHY Control
4486 + CTL_SMC_PHY_STAT, // PHY Status
4487 + CTL_SMC_PHY_ID1, // PHY ID1
4488 + CTL_SMC_PHY_ID2, // PHY ID2
4489 + CTL_SMC_PHY_ADC, // PHY Advertise Capability
4490 + CTL_SMC_PHY_REMC, // PHY Advertise Capability
4491 + CTL_SMC_PHY_CFG1, // PHY Configuration 1
4492 + CTL_SMC_PHY_CFG2, // PHY Configuration 2
4493 + CTL_SMC_PHY_INT, // PHY Interrupt/Status Output
4494 + CTL_SMC_PHY_MASK, // PHY Interrupt/Status Mask
4496 + // ---------------------------------------------------
4497 + CTL_SMC_LAST_ENTRY // Add new entries above the line
4499 +#endif // CONFIG_SYSCTL
4500 +#endif /* _SMC_91111_H_ */